Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory

Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Volumn , Issue , 2009, Pages 166-176

  Mehrara, Mojtaba ^a   Hao, Jeff ^a   Hsu, Po Chun ^a   Mahlke, Scott ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Automatic parallelization; Loop level parallelism; Profile guided optimization; Software transactional memory; Thread level speculation

Indexed keywords

AUTOMATIC PARALLELIZATION; COMMODITY HARDWARE; DATA PARALLEL; DESIGN PARADIGM; EXPENSIVE HARDWARE; LIGHT WEIGHT; LOOP-LEVEL PARALLELISM; MICROPROCESSOR INDUSTRY; MULTI CORE; MULTICORE DESIGN; OPTIMIZATION SOFTWARE; OPTIMIZERS; PARALLELIZATIONS; PARALLELIZING; PERFORMANCE GAIN; RUNTIMES; SEQUENTIAL APPLICATIONS; SOFTWARE SUPPORT; SOFTWARE TRANSACTIONAL MEMORY; THREAD LEVEL SPECULATION; TRANSACTION EXECUTION; TRANSACTIONAL MEMORY;

C (PROGRAMMING LANGUAGE); DESIGN; JAVA PROGRAMMING LANGUAGE; LINGUISTICS; MICROPROCESSOR CHIPS; MODEL CHECKING; PROGRAM COMPILERS; QUERY LANGUAGES; STORAGE ALLOCATION (COMPUTER);

COMPUTER SOFTWARE;

EID: 70450267487     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1542476.1542495     Document Type: Conference Paper

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