End-to-end register data-flow continuous self-test

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 105-115

  Carretero, Javier ^a   Chaparro, Pedro ^a   Vera, Xavier ^a   Abella, Jaume ^a   González, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Control logic; Degradation; Design errors; End to end protection; Online testing

Indexed keywords

ACTUAL ERROR; ARITHMETIC CODE; BURN-IN; COMPUTING SYSTEM; CONTROL LOGIC; CONTROL SIGNAL; DATAFLOW; DESIGN ERRORS; EFFECTIVE MECHANISMS; END-TO-END PROTECTION; FIELD ERRORS; FUNCTIONAL UNITS; ISSUE QUEUE; LATENT DEFECTS; LIGHT WEIGHT; LOW COSTS; MICRO ARCHITECTURES; MICROARCHITECTURAL MECHANISM; MOORE'S LAW; ON-LINE TESTING; REGISTER FILES; SELF-TEST; SEMI-CONDUCTOR; SYSTEM DESIGN; TECHNOLOGY SCALING;

COMPUTER SYSTEMS; COSTS; DEGRADATION; ERRORS; PROGRAM PROCESSORS;

COMPUTER ARCHITECTURE;

EID: 70450230796     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555770     Document Type: Conference Paper

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