Efficient microarchitecture policies for accurately adapting to power constraints

IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

Volumn , Issue , 2009, Pages

  Cebrián, Juan M ^a   Aragón, Juan L ^a   García, José M ^a   Petoumenos, Pavlos ^b   Kaxiras, Stefanos ^b  

^a UNIVERSITY OF MURCIA   (Spain)

^b UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE POWER; BASIC BLOCKS; COARSE-GRAINED TECHNIQUES; DYNAMIC POWER; DYNAMIC VOLTAGE AND FREQUENCY SCALING; ENERGY EFFICIENT; LEAKAGE POWER; MICRO ARCHITECTURES; POWER BUDGETS; POWER CONSTRAINTS; POWER SPIKES; POWER-SAVING; PROCESS TECHNOLOGIES; PROCESSOR POWER CONSUMPTION; STATIC POWER; SUPPLY VOLTAGES; TOTAL ENERGY; TWO-LEVEL APPROACH;

DISTRIBUTED PARAMETER NETWORKS; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY;

BUDGET CONTROL;

EID: 70450091396     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2009.5161022     Document Type: Conference Paper

References (19)

1. Isci, C.; Buyuktosunoglu, A.; Cher, C.; Bose, P. and Martonosi, M. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. In Proc. of the 39th Int. Symposium on Microarchitecture,2006.
2. Aragon, J.L.; Gonzalez, J and Gonzalez, A. Poweraware control speculation thought selective throttling. In Proc. of the 9th Int. Symp. on High-Performance Computer Architecture,2003.
3. Kesharvarzi, A. Intrinsic iddq: Origins, reduction, and applications in deep sub-micron low-power CMOSIC's.In Proc. of the IEEE International Test Conference,1997.
4. Kim, N.S.; Austin, T. et al. Leakage Current: Moore's Law Meets Static Power.In IEEE Computer,vol.36, issue.12 2003.
5. Flynn, M.J. and Hung P. Microprocessor Design Issues: Thoughts on the Road Ahead. In IEEE Micro,vol.25, no. 3, pp. 16-31, May/Jun, 2005.
6. Semeraro, G.; Magklis, G. et al. Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. In Proc. of the 8th Int.Symp. on High-Performance Computer Architecture, 2002.
7. Wu, Q.; Juang, P.; Martonosi, M. and Clark, D. W. Formal Online Methods for Voltage/Frequency Control in Multiple Clock Domain Microprocessors. In Proc. of the 11th Int. Conf. on Arch. Support for Programming Lang. and Operating Systems(ASPLOS-XI), 2004.
8. Donald, J. and Martonosi, M. Techniques for Multicore Thermal Management: Classification and New Exploration. In Proc. of the 33th Int. Symp. on Computer Architecture(ISCA-33), 2006.
9. Jacobsen, E.; Rotenberg, E. and Smith, J. E.. Assigning Confidence to Conditional Branch Predictions. In Proc.of the Int. Symp. on Microarchitecture, December 1996.
10. Baniasadi, A. and Moshovos, A. Instruction Flow-Based Front-end Throttling for Power-Aware High- Performance Processors. In Proc. of the Int. Symp. on Low Power Elect. and Design. 2001.
11. Tune, E.; Liang, D.; Tullsen, D.M. and Calder, B. Dynamic Prediction of Critical Path Instructions. In Proc. of the 7th Int. Symp. on High-Performance Computer Arch.2001
12. Zhang, Y.; Paritkh, D.; et al. HotLeakage: a temperature-aware model of subthreshold and gate leakage for architects. Technical Report, Dept. Comp. Science, U. Virginia, 2003.
13. Casmira, J. and Grunwald, D. Dynamic Instruction Scheduling Slack. In Proc. of the KoolChips Workshop, 2000.
14. Macken, P.; Degrauwe, M.; Paemel, V. and Oguey, H. A voltage reduction technique for digital systems. In IEEE Int. Solid-State Circuits Conf., pages 238- 239,February 1990.
15. Manne, S.; Klauser, A. and Grunwald, D. Pipeline Gating: Speculation Control For Energy Reduction. In Proc. of the Int. Symp. on Computer Architecture, 1998.
16. Simunic, T.; Benini, L.; Acquaviva, A. and Glynn, P. Dynamic Voltage Scaling and Power Management for Portable Systems. In Proc. of the Design Automation Conference, 2001.
17. Kim, W.; Gupta, M. S. et al. System Level Analysis of Fast, Per-Core DVFS using On-Chip Switching Regulators. In Proc. of the 14th Int. Symp. on High-Perf. Computer Architecture. 2008.
18. Sasanka, R.; Hughes, C. J. and Adve, S.V. Joint Local and Global Hardware Adaptations for Energy. In Proc. of the 10th Intl. Conf. on Arch Support for Programming Languages and Operating Systems,2002.
19. Winter, J.A. and Albonesi, D.H. Addressing Thermal Non-Uniformity in SMT Workloads. In ACM Transactions on Architecture and Code Optimization,Vol. 5, No. 1, May 2008.