Accelerating HMMer on FPGAs using systolic array based architecture

IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

Volumn , Issue , 2009, Pages

  Sun, Yanteng ^a   Li, Peng ^b   Gu, Guochang ^a   Wen, Yuan ^a   Liu, Yuan ^b   Liu, Dong ^b  

^a HARBIN ENGINEERING UNIVERSITY   (China)

^b INTEL CHINA RESEARCH CENTER   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY BASED ARCHITECTURE; BIOINFORMATICS SOFTWARE; COMPUTATION KERNEL; FEED-BACK LOOP; PARALLEL DATA; PARALLELIZATIONS; PRIMARY STRUCTURES; PROPOSED ARCHITECTURES; RAPID GROWTH; TRADITIONAL COMPUTERS;

BIOINFORMATICS; DISTRIBUTED PARAMETER NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIDDEN MARKOV MODELS; NUCLEIC ACID SEQUENCES; NUCLEIC ACIDS; STATE FEEDBACK;

COMPUTER ARCHITECTURE;

EID: 70450080436     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2009.5160927     Document Type: Conference Paper

References (15)

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