A multi-layered XML schema and design tool for reusing and integrating FPGA IP

FPL 09: 19th International Conference on Field Programmable Logic and Applications

Volumn , Issue , 2009, Pages 472-475

  Arnesen, Adam ^a   Rollins, Nathaniel ^a   Wirthlin, Michael ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN LANGUAGES; DESIGN PRODUCTIVITY; DESIGN TOOL; INTEGRATION TOOLS; INTELLECTUAL PROPERTY CORES; IP CORE; IP REUSE; MULTI-LAYERED; MULTIPLE LEVELS; RECONFIGURABLE COMPUTING SYSTEMS; XML SCHEMAS;

DESIGN; INTEGRATION; MARKUP LANGUAGES; XML;

INTERNET PROTOCOLS;

EID: 70450064286     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2009.5272468     Document Type: Conference Paper

References (8)

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