Extending SRT for parallel applications in tiled-CMP architectures

IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

Volumn , Issue , 2009, Pages

  Sánchez, Daniel ^a   Aragón, Juan L ^a   García, José M ^a  

^a UNIVERSITY OF MURCIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL SUPPORT; ATOMIC OPERATION; EXECUTION SPEED; FAULT-TOLERANT; PARALLEL APPLICATION; PROGRAM INSTRUCTIONS; SCALING TECHNOLOGY; SHARED MEMORIES; SOFT ERROR; SUPPLY VOLTAGE REDUCTION;

DISTRIBUTED PARAMETER NETWORKS; ENERGY EFFICIENCY;

ERROR CORRECTION;

EID: 70449983725     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2009.5160902     Document Type: Conference Paper

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