Design of a parallel AES for graphics hardware using the CUDA framework

IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

Volumn , Issue , 2009, Pages

  Biagio, Andrea Di ^a   Barenghi, Alessandro ^a   Agosta, Giovanni ^a   Pelosi, Gerardo ^b  

^a POLITECNICO DI MILANO   (Italy)

^b UNIVERSITY OF BERGAMO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SCENARIO; COST BASIS; CRYPTOGRAPHIC PRIMITIVES; DEGREE OF PARALLELISM; GENERAL PURPOSE; GRAPHICS HARDWARE; HARDWARE RESOURCES; MULTI-CORE PROCESSOR; OPEN SSL; PROGRAMMING KNOWLEDGE; QUANTITATIVE DATA; THROUGHPUT IMPROVEMENT; WEB SERVERS;

CRYPTOGRAPHY; DISTRIBUTED PARAMETER NETWORKS;

COMPUTER HARDWARE;

EID: 70449969888     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2009.5161242     Document Type: Conference Paper

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