3D integration process flow for set-top box application: Description of technology and electrical results

2009 European Microelectronics and Packaging Conference, EMPC 2009

Volumn , Issue , 2009, Pages

  Cheramy, S ^a   Charbonnier, J ^a   Henry, D ^a   Astier, A ^a   Chausse, P ^a   Neyret, M ^a   Brunet Manquat, C ^a   Verrun, S ^a   Sillon, N ^a   Bonnot, L ^b   Gagnard, X ^b   Vittu, J ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Stacking; Trough silicon vias (TSV); Wafer level packaging

Indexed keywords

3-D INTEGRATION; 45 NM-NODE TECHNOLOGY; CHIP STACKING; HIGH ASPECT RATIO; NODE TECHNOLOGY; PROCESS FLOWS; PROCESS STEPS; SET TOP BOX; TROUGH SILICON VIAS (TSV); WAFER LEVEL PACKAGING; WAFER-LEVEL PACKAGING TECHNOLOGY;

ASPECT RATIO; CHIP SCALE PACKAGES; DEBONDING; INTERCONNECTION NETWORKS; MICROELECTRONICS; NANOTECHNOLOGY; PACKAGING; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

WAFER BONDING;

EID: 70449737499     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. L. Bonnot & Al, "3D integration program overview", DATE 2009, April 2009.
2. A. Jouve & Al, "Facilitating Ultrathin Wafer Handling for TSV Processing", EPTC 2008, 9-12 december 2008, Singapour.
3. S. Pargfrieder & Al, "3D Integration by Through-Silicon-Via (TSV) processing enabled by Temporary Bonding and Debonding Technology", Advanced Packaging, April 2009 issue.
4. D.Henry & Al, "Through silicon vias technology for cmos image sensors packaging: presentation of technology and electrical results", EPTC 2008, 9-12 december 2008, Singapour.
5. J. Charbonnier & Al, "Integration of a temporary carrier in a TSV Process Flow", EC TC 2009, 26-29 May 2009