A low leakage low cost-PMOS based power supply clamp with active feedback for ESD protection in 65nm CMOS technologies

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2005, Pages

  Smith, Jeremy C ^a   Cline, Roger A ^b   Boselli, Gianluca ^c  

^a ASIC Circuit Design Group   (United States)

^b MS 8661   (United States)

^c Silicon Technology Development   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; ACTIVE FEEDBACK; CMOS PROCESSS; ESD PROTECTION; LOW COSTS; LOW LEAKAGE; POWER SUPPLY; POWER SUPPLY PROTECTION CLAMP; STATE OF THE ART; TRANSIENT LATCH-UP;

ELECTRIC POWER TRANSMISSION NETWORKS; ELECTRIC POWER UTILIZATION; ELECTROSTATIC DEVICES;

ELECTROSTATIC DISCHARGE;

EID: 70449727786     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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