Physics and design optimization of ESD diode for 0.13μm PD-SOI technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2005, Pages

  Entringer, Christophe ^a   Flatresse, Philippe ^a   Salome, Pascal ^a   Nouet, Pascal ^b   Azais, Florence ^b  

^a STMICROELECTRONICS   (France)

^b CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN OPTIMIZATION; ESD PERFORMANCE; GATE COUPLING; GATE LENGTH; GATED DIODES; OXIDE THICKNESS; PARTIALLY DEPLETED SOI; SOI TECHNOLOGY; TCAD SIMULATION;

ELECTROSTATIC DEVICES; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY;

ELECTROSTATIC DISCHARGE;

EID: 70449718964     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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