A task-centric memory model for scalable accelerator architectures

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 77-87

  Kelm, John H ^a   Johnson, Daniel R ^a   Lumetta, Steven S ^a   Frank, Matthew I ^a   Patel, Sanjay J ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATOR ARCHITECTURES; ADDRESS SPACE; COMMUNICATION PATTERN; CORE PROCESSORS; DATA SHARING; LOCAL CACHE; MANAGEMENT POLICY; MEMORY MODELS; MEMORY SYSTEMS; OFF-CHIP; PREFETCHING; RUNTIME SYSTEMS; SHARED CACHE; SOFTWARE MANAGEMENT; SOFTWARE PROTOCOLS; VISUAL COMPUTING;

COMPUTER SOFTWARE; CONSTRAINED OPTIMIZATION; PARALLEL ARCHITECTURES;

SIMULATORS;

EID: 70449671562     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.16     Document Type: Conference Paper

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