Field-split parallel architecture for high performance multi-match packet classification using FPGAs

Annual ACM Symposium on Parallelism in Algorithms and Architectures

Volumn , Issue , 2009, Pages 188-196

  Jiang, Weirong ^a   Prasanna, Viktor K ^a  

^a University of Southern California   (United States)

Author keywords

FPGA; Multi match packet classification; NIDS; SRAM

Indexed keywords

BIT VECTOR; CLOCK RATE; CRITICAL FUNCTIONS; DYNAMIC UPDATE; FPGA TECHNOLOGY; HIGH THROUGHPUT; IN-NETWORK; MATCHING RULES; MEMORY REQUIREMENTS; MULTI-MATCH PACKET CLASSIFICATION; PACKET HEADER; POWER CONSUMPTION; PROPOSED ARCHITECTURES; RULE SET; SUBFIELDS; TERNARY CONTENT ADDRESSABLE MEMORIES;

COMPUTER CRIME; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERNET; INTRUSION DETECTION; PARALLEL ARCHITECTURES; STATIC RANDOM ACCESS STORAGE;

PACKET NETWORKS;

EID: 70449643048     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1583991.1584044     Document Type: Conference Paper

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