Polyhedral-model guided loop-nest auto-vectorization

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 327-337

  Trifunovic, Konrad ^b   Nuzman, Dorit ^a   Cohen, Albert ^b   Zaks, Ayal ^a   Rosen, Ira ^a  

^a IBM HAIFA RESEARCH LAB   (Israel)

^b INRIA SACLAY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE PREDICTION; COST MODELS; LOOP TRANSFORMATION; LOOP VECTORIZATION; MULTIPLE TRANSFORMATION; OPTIMIZING COMPILERS; PERFORMANCE IMPACT; POLYHEDRAL FRAMEWORK; POLYHEDRAL MODELS; POLYHEDRAL REPRESENTATION; PREDICTIVE MODELLING; VECTORIZATION;

PARALLEL ARCHITECTURES;

EID: 70449626135     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.18     Document Type: Conference Paper

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