Wafer and die bonding technologies for 3D integration

Materials Research Society Symposium Proceedings

Volumn 1112, Issue , 2009, Pages 55-65

  Farrens, Shari ^a  

^a SUSS MicroTec Lithography GmbH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; CMOS DEVICES; DIE BONDING; DIE SIZE; DIE STACKING; ENHANCED TRANSMISSION; EQUIPMENT CHOICE; FORM FACTORS; HETEROGENEOUS INTEGRATION; KNOWN-GOOD DIES; LOWER-POWER CONSUMPTION; PERFORMANCE GAIN; PROCESS FLOWS; PROCESS SOLUTIONS; PROCESSING FLOW; SUBSTRATE SIZES; VERTICAL STACKING; WAFER LEVEL; WAFER TECHNOLOGY; WAFER TO WAFER BONDING;

APPROXIMATION THEORY; BONDING; DIES; INTEGRATION; SUBSTRATES; TECHNOLOGY; THREE DIMENSIONAL;

WAFER BONDING;

EID: 70449598031     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Yole Developpement 2007 MEMS Industry Report. http://www.yole.fr/ pagesAn/products/report-MEMS.asp
2. http://www.set-sas.fr/en/multipage.xml?pg=1&id=173582.
3. W. Silver, "The evaluation and design of a Universal Alignment Target", rev 2.0, March 12, 2000.
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5. P. Garrou, "Handbook of 3D Integration", (Wiley, Weinheim Germany, 2008).
6. D. Gupta et al., Chapter 7 "Grain Boundary Diffusion" Thin Films Interdiffusion and Reactions edited by J. M. Poate, K. N. Tu and 1. W. Mayer, (Wiley, New York, 1978) p. 164.
7. Courtesy of STS (UK).
8. P.-I Wang et. al., "Low Temperature Copper-Nanorod Bonding for 3D Integration", (Mater. Res. Soc. Symp. Proc. 970, Pittsburgh, PA, 2007).
9. P. Enquist, "Direct Bond Interconnect (DB1™) - Technology for Scaleable 3D SoCs", (RT1 Conference Proceedings on Semiconductor Integration and Packaging Accessing Technological Developments, Applications, and Key Enablers, Burlingame, California, Oct. 31-Nov. 2, 2006).