A novel LV LP CMOS internal topology of CCII+ and its application in current-mode integrated circuits

2009 Ph.D. Research in Microelectronics and Electronics, PRIME 2009

Volumn , Issue , 2009, Pages 132-135

  Di Carlo, C ^a   De Marcellis, A ^a   Stornelli, V ^a   Ferri, G ^a   Tiberio, D ^a  

^a UNIVERSITY OF L'AQUILA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMMON DRAIN; CURRENT MODE; DIFFERENTIAL PAIRS; FREQUENCY DOMAINS; GENERAL PURPOSE; HIGH IMPEDANCE; IMPEDANCE SIMULATORS; INTERNAL ARCHITECTURE; INTERNAL CIRCUITS; LOW POWER; LOW SUPPLY VOLTAGES; LOW-VOLTAGE; PARASITIC COMPONENTS; PORTABLE APPLICATIONS; SECOND GENERATION CURRENT CONVEYORS; SIGNAL PROCESSING CIRCUITS; STANDARD CMOS TECHNOLOGY; TOTAL POWER CONSUMPTION; TRANSISTOR SIZE;

ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; MICROELECTRONICS; SIGNAL PROCESSING; TOPOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 70449512694     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RME.2009.5201310     Document Type: Conference Paper

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