Partially depleted SOI body-contacted MOSFET-triggered silicon controlled rectifier for ESD protection

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2006, Pages 166-171

  Entringer, Christophe ^a   Flatresse, Philippe ^a   Galy, Philippe ^a   Azais, Florence ^b   Nouet, Pascal ^b  

^a STMICROELECTRONICS   (France)

^b CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ESD PROTECTION; LOW-LEAKAGE CURRENT; MOS-FET; PARTIALLY DEPLETED SOI; POLYSILICON GATES; SILICON CONTROLLED RECTIFIER;

ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; MOSFET DEVICES; POLYSILICON; SILICON ON INSULATOR TECHNOLOGY;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 70449392858     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EOSESD.2006.5256783     Document Type: Conference Paper

References (6)

1. Ajith Amerasekera and Charvaka Duvvury, "ESD in Silicon Integrated Circuits". Wiley second edition, 2003, ch. 6.6, pp. 150-158. ISBN 0471-49871-8
2. S.L. Jang, L.S. Lin, S.H. Li, "Temperature-dependent dynamic triggering characteristics in SCR-type ESD protection circuits", 2001, Solid-State Electronics 45, pp. 2005-2009
3. Olivier Marichal, Geert Wybo, Benjamin Van Camp, Pieter Vanysacker, and Bart Keppens, "SCR based ESD protection in nanometer SOI technologies", EOS/ESD symposium 2005, pp. 372-379
4. Christophe Entringer, Philippe Flatresse, Pascal Salome, Pascal Nouet and Florence Azais "Physics and Design Optimization of ESD diode for 0.13um PD-SOI Technology", EOS/ESD symposium 2005, pp. 53-59
5. Silicon-On-Insulator Technology and Devices, edited by Sorin Cristoloveanu, pp. 287-289, ISBN 1-56677-043-2
6. nd workshop DCAS, 2001, pp. 31-34, 2001