A 10-GB/s burst-mode limiting amplifier using a two-stage active feedback circuit

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 18-19

  Nogawa, Masafumi ^a   Nishimura, Kazuyoshi ^a   Terada, Jun ^a   Nakamura, Makoto ^a   Nishihara, Susumu ^a   Ohtomo, Yusuke ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Burst mode and 10G EPON; Limiting amplifier

Indexed keywords

10 GB/ S; ACTIVE FEEDBACK; BURST MODE AND 10G-EPON; BURST-MODE; DYNAMIC RANGE; LIMITING AMPLIFIER; LIMITING AMPLIFIERS; RECEIVER OPTICAL SUBASSEMBLIES; SETTLING TIME; TWO STAGE; TWO-STAGE AMPLIFIERS; VOLTAGE OFFSETS;

OPTICAL COMMUNICATION; PASSIVE NETWORKS; VLSI CIRCUITS;

AMPLIFIERS (ELECTRONIC);

EID: 70449376822     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. IEEE P802.3av 10GEPON Task Force, http://www.ieee802.org/3/av/index.html.
2. Q. Le, et al., "A CMOS Burst-Mode TIA with Step AGC and Selective Internally Created Reset for 1.25Gb/s EPON," ISSCC Dig. Tech. Papers, pp. 50-51, Feb., 2007.
3. S. Nishihara, et al., "A burst-mode 3R receiver for 10-Gbit/s PON systems with high sensitivity, wide dynamic range, and fast response," IEEE J. Lightwave. Technol., vol. 26, no. 1, pp. 99-107, Jan. 2008.
4. J. Terada, et al., "A 10.3125-Gb/s Burst-Mode CDR using δS DAC," ISSCC Dig. Tech. Papers, pp. 226-227, Feb., 2008.