A 10MHz 80uμW 67 ppm/°C CMOS reference clock oscillator with a temperature compensated feedback loop in 0.18uμm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 226-227

  Lee, Junghyup ^a   Cho, SeongHwan ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Clock; CMOS; Frequency; Low power; Oscillator; Temperature compensation

Indexed keywords

CMOS; FREQUENCY; LOW POWER; OSCILLATOR; TEMPERATURE COMPENSATION;

CLOCKS; SENSITIVITY ANALYSIS; TEMPERATURE DISTRIBUTION; VLSI CIRCUITS;

TIMING CIRCUITS;

EID: 70449337762     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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4. A. V. Boas, et al., "A Temperature Compensated Digitally Trimmable On-Chip IC Oscillator with Low Voltage Inhibit Capability," Proc. ISCAS, pp.501-504, Sep. 2004.
5. S. Sidiropoulos, et al., "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers," Symposium on VLSI Circuits, pp. 124-127, 2000.
6. K. N. Leung, et al., "A Sub-1-V 15-ppm/°C CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Device," IEEE J. Solid-State Circuits, vol. 37, pp. 526-530, Apr. 2002.