VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs

2009 IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2009

Volumn , Issue , 2009, Pages 104-107

  Banga, Mainak ^a   Hsiao, Michael S ^a  

^a State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INVERSION TECHNIQUES; POWER CONSUMPTION; PRIMARY OUTPUTS; VECTOR SIMULATION;

EID: 70449127255     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HST.2009.5224960     Document Type: Conference Paper

References (12)

1. F. Wolff, C. Papachristou, S. Bhunia and R. S. Chakraborty, Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme, DATE, 2008, pp. 1362-1365.
2. G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan and J. Rajski; Logic BIST for large industrial designs: real issues and case studies, ITC, 1999, pp. 358-367.
3. D. Agarwal, B. Archambeault, J. R. Rao and P. Rohatgi, The EM sidechannel( s), Int. Workshop CHES, 2002, Vol. 2523, pp. 29-45.
4. P. C. Kocher, Timing attacks on implantations of diffiehellman, rsa, dss and other systems in Neal Kobitz, Proc. of CRYPTO, Vol. 1109 of Lecture Notes in Computer Science, pp. 104-113.
5. I. Verbauwhede, K. Tiri, D. Hwang, and P. Schaumont, Circuits and design techniques for secure ICs resistant to side-channel attack, Int. Conf. on IC Design and Technology, 2006, pp. 1-4.
6. J. Guajardo, S. S. Kumar, G. J. Schrijen and P. Tuyls, Physical Unclonable Functions and Public-Key Crypto for FPGA IP Protection, Int. Conf. on Field Prog. Logic and App., Aug. 2007, pp. 189-195.
7. D. Agarwal et al.; Trojan Detection using IC Fingerprinting, Proc. of the Symposium on Security and Privacy, 2007, pp. 296-310.
8. R. Rad, J. Plusquellic and M. Tehranipoor, Sensitivity analysis to hardware Trojans using power supply transient signals, HOST, 2008, pp. 3-7.
9. M. Banga and M. Hsiao; A Region Based Approach for the Detection of Hardware Trojans, HOST, 2008, pp. 43-50.
10. M. Banga and M. Hsiao; A Novel Sustained Vector Technique for the Detection of Hardware Trojans, VLSI Design, 2009, pp. 327-332.
11. Neil H. E. Weste and D. Harris, CMOS VLSI Design: A circuits and Systems Perspective, IIIed, Pearson Education (Addison Wesley), 2005.
12. S. Narendra, V. De, S. Borkar, D. Antoniadis, A. Chandrakasan, Fullchip sub-threshold leakage power prediction model for sub-0.18nm CMOS, International Symposium on Low Power Electronics and Design, 2002, pp. 19 - 23.