Verification of process operations using model checking

2009 IEEE International Conference on Automation Science and Engineering, CASE 2009

Volumn , Issue , 2009, Pages 415-420

  Voronov, Alexey ^a   Åkesson, Knut ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL LOGIC; DEVELOPMENT PROCESS; FORMAL VERIFICATIONS; HIGH LEVEL SPECIFICATION; NON-BLOCKING; POTENTIAL ERRORS; PROCESS OPERATION; SUPERVISORY CONTROL; SYMBOLIC MODEL CHECKING; TIME TO MARKET;

CONCURRENT ENGINEERING; SPECIFICATIONS; TRANSLATION (LANGUAGES);

MODEL CHECKING;

EID: 70449103235     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/COASE.2009.5234103     Document Type: Conference Paper

References (8)

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