Aliasing-free compaction in testing cores-based system-on-chip (SOC) using compatibility of response data outputs

Journal of Integrated Design and Process Science

Volumn 8, Issue 1, 2004, Pages 1-17

  Das, Sunil R ^a,b   Assaf, Mansour H ^a   Petriu, Emil M ^a   Sahinoglu, Mehmet ^b  

^a UNIVERSITY OF OTTAWA   (Canada)

^b TROY UNIVERSITY   (United States)

Author keywords

Aliasing free (zero aliasing) space compaction; Built in self testing (BIST) in VLSI; Compatibility of response data outputs; Cores based system on chip (SOC); Module under test (MUT)

Indexed keywords

ALGORITHMS; BENCHMARKING; COMPACTION; COMPUTER SIMULATION; DATA ACQUISITION; DATA STORAGE EQUIPMENT; FLIP CHIP DEVICES; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; NATURAL FREQUENCIES; SWITCHING; VLSI CIRCUITS; BUILT-IN SELF TEST; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT TESTING; PROGRAMMABLE LOGIC CONTROLLERS; SEMICONDUCTOR DEVICE MANUFACTURE; SEQUENTIAL MACHINES;

ALIASING-FREE SPACE COMPACTION; COMPATIBILITY OF RESPONSE DATA OUTPUTS; CORES-BASED SYSTEM-ON-CHIP (SOC); MODULE UNDER TEST (MUT);

BUILT-IN SELF TEST; SYSTEM-ON-CHIP;

ALIASING; ALIASING-FREE (ZERO-ALIASING) SPACE COMPACTION; BUILD-IN SELF-TESTING IN VLSI; BUILT-IN SELF-TESTING; COMPATIBILITY OF RESPONSE DATA OUTPUT; CORE BASED SYSTEM ON CHIPS; CORE-BASED SYSTEM-ON-CHIP; CORES BASED SYSTEM ON CHIPS; DATA OUTPUT; MODULE UNDER TEST; MODULE UNDER TESTS; RESPONSE DATA; SPACE COMPACTION; ZERO ALIASING;

EID: 7044222783     PISSN: 10920617     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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