Defect-tolerant N2-transistor structure for reliable nanoelectronic designs

IET Computers and Digital Techniques

Volumn 3, Issue 6, 2009, Pages 570-580

  El Maleh, A H ^a   Al Hashimi, B M ^b   Melouki, A ^b   Khan, F ^a  

^a KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS   (Saudi Arabia)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS AND SIMULATION; AREA OVERHEAD; BENCHMARK CIRCUIT; CIRCUIT DESIGNS; DEFECT PROBABILITY; DEFECT TOLERANCE; EXTENSIVE SIMULATIONS; NANO-DEVICES; TRANSISTOR LEVEL; TRANSISTOR STRUCTURE;

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; NANOELECTRONICS; TRANSISTORS;

DEFECT STRUCTURES;

EID: 70350726543     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2008.0133     Document Type: Article

References (17)

1. Butts, M., DeHon, A., and Goldstein, S.C.: ' Molecular electronics: devices, systems and tools for gigagate, gigabit chips ', ICCAD, 2002, p. 433-440
2. Bachtold, T.N.A., Harley, P., and Dekker, C.: ' Logic circuits with carbon nanotube transistors ', Science, 2001, 294, p. 1317-1320 10.1126/science.1065824 0036-8075 (Pubitemid 33063092)
3. Cui, Y., and Lieber, C.M.: ' Functional nanoscale electronic devices assembled using silicon nanowire building blocks ', Science, 2001, 291, p. 851-853 10.1126/science.291.5505.851 0036-8075 (Pubitemid 32120751)
4. Huang, Y.: ' Logic gates and computation from assembled nanowire building blocks ', Science, 2001, 294, p. 1313-1317 10.1126/science.1066192 0036-8075 (Pubitemid 33063091)
5. Tougaw, P.D., and Lent, C.S.: ' Logical devices implemented using quantum cellular automata ', J. Appl. Phys., 1994, 75, p. 1818-1825 0021-8979
6. Chen, Y., Jung, G.-Y., and Ohlberg, D.A.A.: et al. ' Nanoscale molecular-switch crossbar circuits ', Nanotechnology, 2003, 14, (4), p. 462-468 10.1088/0957-4484/14/4/311 0957-4484
7. Whang, D., Jin, S., Wu, Y., and Lieber, C.M.: ' Large-scale hierarchical organization of nanowire arrays for integrated nanosystems ', Nanoletters, 2003, 3, (9), p. 1255-1259
8. He, C., Jacome, M.F., and de Veciana, G.: ' A reconfiguration-based defect-tolerant design paradigm for nanotechnologies ', IEEE Des. & Test Comput., 2005, p. 316-326
9. Han, J., Gao, J., Qi, Y., Jonker, P., and Fortes, J.A.B.: ' Toward hardware-redundant, fault-tolerant logic for nanoelectronics ', IEEE Des. & Test Comput., 2005, p. 328-339
10. Spagocci, S., and Fountain, T.: ' Fault rates in nanochip devices ', Proc. Electrochem. Soc., 1999, 98, (19), p. 582-593
11. Thaker, D.D., Impens, F., Chuang, I.L., Amirtharajah, R., and Chong, F.T.: ' Recursive TMR: scaling fault tolerance in the nanoscale era ', IEEE Des. & Test Comput., 2005, p. 298-305
12. Moore, E.F., and Shannon, C.E.: ' Reliable circuits using less reliable relays ', J. Franklin Inst., 1956, 262, p. 191-197 0016-0032
13. Suran, J.J.: ' Use of circuit redundancy to increase system reliability ', Int. Solid-State Circuits Conf., February, 1964, p. 82-83
14. Lin, Y., Appenzeller, J., Knoch, J., and Avouris, P.: ' High-performance carbon nanotube FET with tunable polarities ', IEEE Trans. Nanotechnol., 2005, 4, (5), p. 481-489 1536-125X
15. Comtet, L.: ' Advanced combinatorics: the art of finite and infinite expansions ', (Reidel Publishing Co., Dordrecht, The Netherlands, 1974), Revised and Enlarged Edition
16. Zhao, C., Dey, S., and Bai, X.: ' Soft-spot analysis: targeting compound noise effects in nanometer circuits ', IEEE Des. & Test Comput., 2005, p. 362-375
17. Hamzaoglu, I., and Patel, J.H.: ' Test set compaction algorithms for combinational circuits ', Proc. Int. Conf. Computer-Aided Design, November, 1998, p. 283-289