-
1
-
-
84939573910
-
Differential Power Analysis, CRYPTO
-
P. Kocher, J. Jaffe, B. Jun, "Differential Power Analysis", CRYPTO, LNCS 1666, pp. 388-397, 1999.
-
(1999)
LNCS
, vol.1666
, pp. 388-397
-
-
Kocher, P.1
Jaffe, J.2
Jun, B.3
-
2
-
-
35048819488
-
Hardware Countermeasures Against DPA - A Statistical Analysis of Their Effectiveness, CT-RSA
-
S. Mangard, "Hardware Countermeasures Against DPA - A Statistical Analysis of Their Effectiveness", CT-RSA, LNCS 2964, pp. 222-235, 2004.
-
(2004)
LNCS
, vol.2964
, pp. 222-235
-
-
Mangard, S.1
-
3
-
-
33744734677
-
A digital design flow for secure integrated circuits
-
K. Tiri, I. Verbauwhede, "A digital design flow for secure integrated circuits," IEEE Transaction on CAD, vol. 25(7), pp. 1197-1208, 2006.
-
(2006)
IEEE Transaction on CAD
, vol.25
, Issue.7
, pp. 1197-1208
-
-
Tiri, K.1
Verbauwhede, I.2
-
4
-
-
27944475547
-
Simulation models for side-channel information leaks
-
K. Tiri, I. Verbauwhede, "Simulation models for side-channel information leaks," ACM/IEEE DAC, pp. 228-233, 2005.
-
(2005)
ACM/IEEE DAC
, pp. 228-233
-
-
Tiri, K.1
Verbauwhede, I.2
-
5
-
-
51749110467
-
Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems
-
L. Lin, W. Burleson, "Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems", IEEE ISCAS, pp. 252-255, 2008.
-
(2008)
IEEE ISCAS
, pp. 252-255
-
-
Lin, L.1
Burleson, W.2
-
6
-
-
0036858210
-
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
-
J. Tschanz, J.Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," IEEE Journal of Solid-State Circuits, Vol. 37(11), pp. 1396-1402, 2002.
-
(2002)
IEEE Journal of Solid-State Circuits
, vol.37
, Issue.11
, pp. 1396-1402
-
-
Tschanz, J.1
Kao, J.2
Narendra, S.3
Nair, R.4
Antoniadis, D.5
Chandrakasan, A.6
De, V.7
-
7
-
-
34547251027
-
Side-channel attack pitfalls
-
K. Tiri, "Side-channel attack pitfalls," ACM/IEEE DAC, pp. 15-20, 2007.
-
(2007)
ACM/IEEE DAC
, pp. 15-20
-
-
Tiri, K.1
-
8
-
-
34548719905
-
Trojan detection using IC fingerprinting
-
D. Agrawal, S. Baktir, D. Karakoyunlu, P. Rohatgi, B. Sunar, "Trojan detection using IC fingerprinting," IEEE Symposium on Security and Privacy, pp. 296-310, 2007.
-
(2007)
IEEE Symposium on Security and Privacy
, pp. 296-310
-
-
Agrawal, D.1
Baktir, S.2
Karakoyunlu, D.3
Rohatgi, P.4
Sunar, B.5
-
9
-
-
35248825993
-
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology, CHES
-
K. Tiri, I. Verbauwhede, "Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology," CHES, LNCS, vol. 2779, pp. 125-136, 2003.
-
(2003)
LNCS
, vol.2779
, pp. 125-136
-
-
Tiri, K.1
Verbauwhede, I.2
-
10
-
-
38849202349
-
Secure FPGA circuits using controlled placement and routing
-
P. Yu, P. Schaumont, "Secure FPGA circuits using controlled placement and routing," ACM/IEEE CODES+ISSS, pp. 45-50, 2007.
-
(2007)
ACM/IEEE CODES+ISSS
, pp. 45-50
-
-
Yu, P.1
Schaumont, P.2
-
11
-
-
1542329235
-
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation, ACM/IEEE
-
S. Mukhopadhyay, K. Roy, "Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation," ACM/IEEE ISLPED, pp. 172-175, 2003.
-
(2003)
ISLPED
, pp. 172-175
-
-
Mukhopadhyay, S.1
Roy, K.2
-
12
-
-
1542269365
-
Statistical estimation of leakage current considering inter- and intra-die process variation, ACM/IEEE
-
R. Rao, A. Srivastava, D. Blaauw, D. Sylvester, "Statistical estimation of leakage current considering inter- and intra-die process variation," ACM/IEEE ISLPED, pp. 84-89, 2003.
-
(2003)
ISLPED
, pp. 84-89
-
-
Rao, R.1
Srivastava, A.2
Blaauw, D.3
Sylvester, D.4
-
13
-
-
70350727183
-
-
International Technology Roadmap for Semiconductors, 2006, http://public.itrs.net.
-
(2006)
-
-
-
14
-
-
84886736952
-
New generation of predictive technology model for sub-45nm design exploration
-
W. Zhao, Y. Cao, "New generation of predictive technology model for sub-45nm design exploration," IEEE ISQED, pp. 585-590, 2006.
-
(2006)
IEEE ISQED
, pp. 585-590
-
-
Zhao, W.1
Cao, Y.2
-
16
-
-
48349095147
-
Process variations and process-tolerant design
-
S. Bhunia, S. Mukhopadhyay, K. Roy, "Process variations and process-tolerant design," IEEE VLSI Design, pp. 699-704, 2007.
-
(2007)
IEEE VLSI Design
, pp. 699-704
-
-
Bhunia, S.1
Mukhopadhyay, S.2
Roy, K.3
-
17
-
-
84886448051
-
Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation
-
K. Takeuchi, T. Tatsumi, A. Furukawa, "Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation," IEEE IEDM, pp.841-844, 1997.
-
(1997)
IEEE IEDM
, pp. 841-844
-
-
Takeuchi, K.1
Tatsumi, T.2
Furukawa, A.3
-
18
-
-
0036916414
-
Methods for true power minimization, ACM/IEEE
-
R. Brodersen, M. Horowitz, D. Markovic, B. Nikolic, V. Stojanovic, "Methods for true power minimization", ACM/IEEE ICCAD, pp. 35-42, 2002.
-
(2002)
ICCAD
, pp. 35-42
-
-
Brodersen, R.1
Horowitz, M.2
Markovic, D.3
Nikolic, B.4
Stojanovic, V.5
-
19
-
-
4444245930
-
Selective gate-level biasing for cost-effective runtime leakage control
-
P. Gupta, A. Kahng, P. Sharma, D. Sylvester, "Selective gate-level biasing for cost-effective runtime leakage control," ACM/IEEE DAC, pp. 327-330, 2004.
-
(2004)
ACM/IEEE DAC
, pp. 327-330
-
-
Gupta, P.1
Kahng, A.2
Sharma, P.3
Sylvester, D.4
|