Throughput optimal task allocation under thermal constraints for multi-core processors

Proceedings - Design Automation Conference

Volumn , Issue , 2009, Pages 776-781

  Hanumaiah, Vinay ^a   Rao, Ravishankar ^b   Vrudhula, Sarma ^a   Chatha, Karam S ^a  

^a Arizona State University   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

Multi core processors; Optimal throughput; Task allocation; Thermal management; Thread migration

Indexed keywords

TEMPERATURE CONTROL;

MULTI-CORE PROCESSOR; OPTIMAL THROUGHPUTS; SINGLE-CORE PROCESSORS; SYSTEM'S DYNAMICS; TASK ALLOCATION; THERMAL CONSTRAINTS; THREAD MIGRATION; THROUGHPUT-OPTIMAL;

COMPUTER AIDED DESIGN;

EID: 70350721931     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629911.1630112     Document Type: Conference Paper

References (22)

1. NAS Parallel Benchmarks. http://www.nas.nasa.gov/Resources/Software/npb. html.
2. SPEC CPU2000 Benchmarks. http://www.spec.org/benchmarks.html.
3. S. Borkar. Thousand core chips: A technology perspective. In DAC, pages 746-749, 2007.
4. D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. In Proc. HPCA, pages 171-182, 2001.
5. J. Donald and M. Martonosi. Techniques for multicore thermal management: Classification and new exploration. SIGARCH Comput. Archit. News, 34(2):78-88, 2006.
6. D. Wentzlaff et al. On-chip interconnection architecture of the Tile Processor. IEEE Micro, 27(5):15-31, 2007.
7. K. Skadron et al. Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management. In Proc. HPCA'02, pages 17-28, 2002.
8. M. D. Powell et al. Heat-and-run: Leveraging SMT and CMP to manage power density through the operating system. SIGOPS Oper. Syst. Rev., 38(5):260-270, 2004.
9. M. Monchiero et al. Power/performance/thermal design-space exploration for multicore architectures. IEEE Trans. Parallel Distrib. Syst., 19(5):666-681, 2008.
10. P. Chaparro et al. Understanding the thermal implications of multicore architectures. TPDS, 18(8):1055-1065, 2007.
11. P. Michaud et al. A study of thread migration in temperature-constrained multicores. ACM Trans. Archit. Code Optim., 4(2):9-1-9-28, 2007.
12. S. Murali et al. Temperature-aware processor frequency assignment for MPSoCs using convex optimization. In Proc. CODES+ISSS, pages 111-116, 2007.
13. T. Constantinou et al. Performance implications of single thread migration on a chip multi-core. ACM SIGARCH, 33(4):80-91, 2005.
14. W. Huang et al. An improved block-based thermal model in hotspot 4.0 with granularity considerations. In WDDD, 2007.
15. W. Liao et al. Temperature and supply voltage aware performance and power modeling at microarchitecture level. TCAD, 24(7):1042-1053, 2005.
16. Y. Han et al. Temptor: A lightweight runtime temperature monitoring tool using performance counters. In TACS, pages 17-28, 2006.
17. J. Munkres. Algorithms for the assignment and transportation problems. Journal of the Society for Industrial and Applied Mathematics, 5(1):32-38, 1957.
18. R. Rao. Fast and accurate techniques for early design space exploration and dynamic thermal management of multi-core processors. PhD thesis, Arizona State University, 2008.
19. R. Rao and S. Vrudhula. Performance optimal processor throttling under thermal constraints. In Proc. CASES, pages 257-266, 2007.
20. R. Rao and S. Vrudhula. Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. In Proc. ICCAD, pages 537-542, 2008.
21. Y. Taur. CMOS design near the limit of scaling. IBM J. Res. and Dev., 46(23):213-222, 2002.
22. S. Zhang and K. S. Chatha. Approximation algorithm for the temperature-aware scheduling problem. In Proc. ICCAD, pages 281-288, 2007.