-
1
-
-
24644470145
-
An incremental and layered procedure for the satisfiability of linear arithmetic logic
-
Halbwachs, N, Zuck, L.D, eds, TACAS 2005, Springer, Heidelberg
-
Bozzano, M., Bruttomesso, R., Cimatti, A., Junttila, T., van Rossum, P., Schulz, S., Sebastiani, R.: An incremental and layered procedure for the satisfiability of linear arithmetic logic. In: Halbwachs, N., Zuck, L.D. (eds.) TACAS 2005. LNCS, vol. 3440, pp. 317-333. Springer, Heidelberg (2005)
-
(2005)
LNCS
, vol.3440
, pp. 317-333
-
-
Bozzano, M.1
Bruttomesso, R.2
Cimatti, A.3
Junttila, T.4
van Rossum, P.5
Schulz, S.6
Sebastiani, R.7
-
2
-
-
0025558645
-
Efficient implementation of a BDD package
-
Orlando, FL, June
-
Brace, K.S., Rudell, R.L., Bryant, R.E.: Efficient implementation of a BDD package. In: Proceedings of the 27th Design Automation Conference, Orlando, FL, June 1990, pp. 40-45 (1990)
-
(1990)
Proceedings of the 27th Design Automation Conference
, pp. 40-45
-
-
Brace, K.S.1
Rudell, R.L.2
Bryant, R.E.3
-
3
-
-
33749846787
-
-
Dutertre, B., de Moura, L.: A fast linear-arithmetic solver for DPLL(T). In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, 4144, pp. 81-94. Springer, Heidelberg (2006)
-
Dutertre, B., de Moura, L.: A fast linear-arithmetic solver for DPLL(T). In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, vol. 4144, pp. 81-94. Springer, Heidelberg (2006)
-
-
-
-
4
-
-
26444468031
-
-
Ivančíc, F., Yang, Z., Ganai, M.K., Gupta, A., Shlyakhter, I., Ashar, P.: F-soft: Software verification platform. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, 3576, pp. 301-306. Springer, Heidelberg (2005)
-
Ivančíc, F., Yang, Z., Ganai, M.K., Gupta, A., Shlyakhter, I., Ashar, P.: F-soft: Software verification platform. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, vol. 3576, pp. 301-306. Springer, Heidelberg (2005)
-
-
-
-
5
-
-
24644446561
-
Efficient conflict analysis for finding all satisfying assignments of a Boolean circuit
-
Halbwachs, N, Zuck, L.D, eds, TACAS 2005, Springer, Heidelberg
-
Jin, H., Han, H., Somenzi, F.: Efficient conflict analysis for finding all satisfying assignments of a Boolean circuit. In: Halbwachs, N., Zuck, L.D. (eds.) TACAS 2005. LNCS, vol. 3440, pp. 287-300. Springer, Heidelberg (2005)
-
(2005)
LNCS
, vol.3440
, pp. 287-300
-
-
Jin, H.1
Han, H.2
Somenzi, F.3
-
6
-
-
27944466840
-
Prime clauses for fast enumeration of satisfying assignments to Boolean circuits
-
Anaheim, CA, June
-
Jin, H., Somenzi, F.: Prime clauses for fast enumeration of satisfying assignments to Boolean circuits. In: Proceedings of the Design Automation Conference, Anaheim, CA, June 2005, pp. 750-753 (2005)
-
(2005)
Proceedings of the Design Automation Conference
, pp. 750-753
-
-
Jin, H.1
Somenzi, F.2
-
7
-
-
0029486985
-
Efficient validity checking for processor verification
-
San Jose, CA, November
-
Jones, R.B., Dill, D.L., Burch, J.R.: Efficient validity checking for processor verification. In: Proceedings of the International Conference on Computer-Aided Design, San Jose, CA, November 1995, pp. 2-6 (1995)
-
(1995)
Proceedings of the International Conference on Computer-Aided Design
, pp. 2-6
-
-
Jones, R.B.1
Dill, D.L.2
Burch, J.R.3
-
8
-
-
70350694589
-
-
Karplus, K.: Representing Boolean functions with if-then-else DAGs. In Technical Report UCSC-CRL-88-28, Board of Studies in Computer Engineering, University of California at Santa Cruz, Santa Cruz, CA 95064 (December 1988)
-
Karplus, K.: Representing Boolean functions with if-then-else DAGs. In Technical Report UCSC-CRL-88-28, Board of Studies in Computer Engineering, University of California at Santa Cruz, Santa Cruz, CA 95064 (December 1988)
-
-
-
-
9
-
-
48949097773
-
-
Kim, H., Jin, H., Ravi, K., Spacek, P., Pierce, J., Kurshan, B., Somenzi, F.: Application of formal word-level analysis to constrained random simulation. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, 5123, pp. 487-490. Springer, Heidelberg (2008)
-
Kim, H., Jin, H., Ravi, K., Spacek, P., Pierce, J., Kurshan, B., Somenzi, F.: Application of formal word-level analysis to constrained random simulation. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 487-490. Springer, Heidelberg (2008)
-
-
-
-
10
-
-
70350688358
-
Disequality management in integer difference logic via finite instantiations
-
Kim, H., Jin, H., Somenzi, F.: Disequality management in integer difference logic via finite instantiations. Journal on Satisfiability, Boolean Modeling and Computation 3, 47-66 (2007)
-
(2007)
Journal on Satisfiability, Boolean Modeling and Computation
, vol.3
, pp. 47-66
-
-
Kim, H.1
Jin, H.2
Somenzi, F.3
-
12
-
-
26444452555
-
-
Nieuwenhuis, R., Oliveras, A.: DPLL(T) with exhaustive theory propagation and its application to difference logic. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, 3576, pp. 321-334. Springer, Heidelberg (2005)
-
Nieuwenhuis, R., Oliveras, A.: DPLL(T) with exhaustive theory propagation and its application to difference logic. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, vol. 3576, pp. 321-334. Springer, Heidelberg (2005)
-
-
-
-
13
-
-
33749821236
-
-
Roe, K.: The heuristic theorem prover: Yet another SMT modulo theorem prover. In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, 4144, pp. 467-470. Springer, Heidelberg (2006)
-
Roe, K.: The heuristic theorem prover: Yet another SMT modulo theorem prover. In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, vol. 4144, pp. 467-470. Springer, Heidelberg (2006)
-
-
-
-
14
-
-
84869654181
-
-
http://smtcomp.org/
-
-
-
-
15
-
-
84869638021
-
-
http://vlsi.colorado.edu/~vis
-
-
-
-
16
-
-
84869653430
-
-
http://yices.csl.sri.com
-
-
-
-
17
-
-
33749582869
-
-
Yu, Y., Malik, S.: Lemma learning in SMT on linear constraints. In: Biere, A., Gomes, C.P. (eds.) SAT 2006. LNCS, 4121, pp. 142-155. Springer, Heidelberg (2006)
-
Yu, Y., Malik, S.: Lemma learning in SMT on linear constraints. In: Biere, A., Gomes, C.P. (eds.) SAT 2006. LNCS, vol. 4121, pp. 142-155. Springer, Heidelberg (2006)
-
-
-
|