Energy efficient architecture of sensor network node based on compression accelerator

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2009, Pages 117-120

  Wang, Jue ^a   Ying, Beihua ^a   Liu, Yongpan ^a   Yang, Huazhong ^a   Wang, Hui ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Chip design; Compression accelerator; Energy efficient; Wireless sensor network

Indexed keywords

BASEBAND CHIPS; CHIP DESIGN; CMOS TECHNOLOGY; COMPRESSION ACCELERATOR; ENERGY CONSUMPTION; ENERGY EFFICIENT; ENERGY-EFFICIENT ARCHITECTURES; GENERAL PURPOSE PROCESSORS; HARDWARE ACCELERATORS; LOW ENERGY CONSUMPTION; SENSOR NETWORK NODES; WAVELET COMPRESSION ALGORITHM; WIRELESS SENSOR;

ACCELERATION; CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; GENERAL PURPOSE COMPUTERS; LAKES; SENSOR NETWORKS; SENSOR NODES; TELECOMMUNICATION EQUIPMENT; WIRELESS TELECOMMUNICATION SYSTEMS;

WIRELESS SENSOR NETWORKS;

EID: 70350604250     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1531542.1531572     Document Type: Conference Paper

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