Multicast routing with dynamic packet fragmentation

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2009, Pages 113-116

  Kang, Young Hoon ^a   Sondeen, Jeff ^a   Draper, Jeff ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Interconnection Network; NoC; On chip router

Indexed keywords

90 NM TECHNOLOGY; CHIP MULTIPROCESSOR; COHERENCE PROTOCOL; CRITICAL DESIGN; HIGH BANDWIDTH; MANY-CORE; MULTICAST CAPABILITIES; MULTICAST ROUTERS; MULTICAST ROUTING; NETWORK LOAD; NETWORKS ON CHIPS; NOC; ON-CHIP NETWORKS; ON-CHIP ROUTER; PACKET FRAGMENTATION; SCALE-UP; SYSTEMS-ON-A-CHIP; UNICAST; VIRTUAL CHANNELS;

CIRCUIT SIMULATION; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; INTERCONNECTION NETWORKS; LAKES; MICROPROCESSOR CHIPS; MULTICASTING; NETWORK PROTOCOLS; ROUTING ALGORITHMS;

ROUTERS;

EID: 70350584637     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1531542.1531571     Document Type: Conference Paper

References (11)

1. R.V. Boppana et al. Resource Deadlocks and Performance of Wormhole Multicast Routing Algorithms. In IEEE Trans. on Parallel and Distributed Systems, Vol.9, pp. 535-549, Jun, 1998.
2. X. Lin et al. Deadlock-Free Multicast Wormhole Routing in 2D Mesh Multicomputers. In IEEE Trans. on Parallel and Distributed Systems, Vol.5, pp. 793-804, Aug, 1994.
3. M.P. Malumbres, J. Duato, and J. Torrellas. An Efficient Implementation of Tree-Based Multicast Routing for Distributed Shared-Memory Multiprocessors. In Proc. of International Symposium on Parallel and Distributed Processing, Oct, 1996.
4. Z. Lu et al. Connection-oriented Multicasting in Wormhole-switched Networks on Chip. In Proc. Emerging VLSI Technologies and Architectures, Mar, 2006.
5. A. Kumar et al. A 4.6Tbits/s 3.6GHz Single-cycle NoC Router with a Novel Switch Allocator in 65nm CMOS. In Proc. of International Conference on Computer Design, Oct, 2007.
6. D. R. Kumar. A New Adaptive Hardware Tree-Based Multicast Routing in K-ary N-Cubes. In IEEE Trans. on Computers, Vol.50, No.7, pp. 647-659, Jul, 2001.
7. C. .M. Chiang and L.M. Ni. Multi-Address Encoding for Multicast. In Proc. of the Parallel Computer Routing and Communication Workshop, pp. 146-160, May, 1994.
8. J. D. Owens et al. Research Challenges for On-Chip Interconnection Networks. In IEEE Micro, Sep, 2007.
9. W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Pub., 2003.
10. N.E. Jerger et al. Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support. In Proc. of International Symposium on Computer Architecture, Jun, 2008.
11. T. Bjerregaard and S. Mahadevan. A Survey of Research and Practices of Network-on-Chip. ACM Computing Surveys, Vol.38, March, 2006.