Hardware supported time synchronization in multi-core architectures

Proceedings - Workshop on Principles of Advanced and Distributed Simulation, PADS

Volumn , Issue , 2009, Pages 88-94

  Lynch, Elizabeth Whitaker ^a   Riley, George F ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER SYNCHRONIZATION; CONSERVATIVE SYNCHRONIZATION; GLOBAL STATE INFORMATION; GLOBAL SYNCHRONIZATION; LOOK-AHEAD; MULTICORE ARCHITECTURES; NETWORK SIMULATION; NONUNIFORM; ON CHIPS; PARALLEL SIMULATIONS; RUNTIMES; SHARED MEMORIES; SYSTEM SIMULATOR; TIME SYNCHRONIZATION;

COMPUTER ARCHITECTURE; COMPUTER SIMULATION;

SYNCHRONIZATION;

EID: 70350378655     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PADS.2009.19     Document Type: Conference Paper

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