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Volumn 10, Issue , 1993, Pages 535-576

13 VLSI implementations of number theoretic concepts with applications in signal processing

(3)  Jullien, G A a   Wigley, N M a   Reilly, J a  

a NONE

Author keywords

[No Author keywords available]

Indexed keywords


EID: 70350347454     PISSN: 01697161     EISSN: None     Source Type: Book Series    
DOI: 10.1016/S0169-7161(05)80079-3     Document Type: Review
Times cited : (2)

References (20)
  • 2
    • 0022769976 scopus 로고
    • Graph-based algorithms for boolean function manipulation
    • Bryant R.E. Graph-based algorithms for boolean function manipulation. IEEE Trans. Comput. 35 (1986) 677-691
    • (1986) IEEE Trans. Comput. , vol.35 , pp. 677-691
    • Bryant, R.E.1
  • 3
    • 0022867125 scopus 로고
    • Design procedures for differential cascode-voltage switch circuits
    • Chu M.K., and Pulfrey D.I. Design procedures for differential cascode-voltage switch circuits. IEEE Trans. Solid-State Circuits. 21 (1986) 1082-1087
    • (1986) IEEE Trans. Solid-State Circuits. , vol.21 , pp. 1082-1087
    • Chu, M.K.1    Pulfrey, D.I.2
  • 4
    • 11944254646 scopus 로고
    • Hermann, New York
    • Godement R. Algebra (1968), Hermann, New York
    • (1968) Algebra
    • Godement, R.1
  • 6
    • 0017956245 scopus 로고
    • Residue number scaling and other operations using ROM arrays
    • Jullien G.A. Residue number scaling and other operations using ROM arrays. IEEE Trans. Comput. 27 (1978) 325-336
    • (1978) IEEE Trans. Comput. , vol.27 , pp. 325-336
    • Jullien, G.A.1
  • 7
    • 51249172205 scopus 로고
    • An efficient bit-level systolic cell design for finite ring digital signal processing applications
    • Jullien G.A., Bird P.D., Carr J.T., Taheri M., and Miller W.C. An efficient bit-level systolic cell design for finite ring digital signal processing applications. J. VLSI Sig. Proc. 1 (1989) 189-208
    • (1989) J. VLSI Sig. Proc. , vol.1 , pp. 189-208
    • Jullien, G.A.1    Bird, P.D.2    Carr, J.T.3    Taheri, M.4    Miller, W.C.5
  • 9
    • 0020098985 scopus 로고
    • Implementation of signal processing functions using 1-bit systolic arrays
    • McCanny J.V., and McWhirter J.G. Implementation of signal processing functions using 1-bit systolic arrays. Electron. Lett. 18 (1982) 241
    • (1982) Electron. Lett. , vol.18 , pp. 241
    • McCanny, J.V.1    McWhirter, J.G.2
  • 13
    • 84932847893 scopus 로고
    • A symbolic analysis of relay and switching circuits
    • Shannon C.E. A symbolic analysis of relay and switching circuits. Trans. AIEE 57 (1938) 713-723
    • (1938) Trans. AIEE , vol.57 , pp. 713-723
    • Shannon, C.E.1
  • 14
    • 0022135064 scopus 로고
    • FET scaling in domino CMOS gates
    • Shoji M. FET scaling in domino CMOS gates. IEEE J. Solid-State Circuits 20 (1985) 1067-1071
    • (1985) IEEE J. Solid-State Circuits , vol.20 , pp. 1067-1071
    • Shoji, M.1
  • 16
    • 0023995237 scopus 로고
    • High speed signal processing using systolic arrays over finite rings
    • Taheri M., Jullien G.A., and Miller W.C. High speed signal processing using systolic arrays over finite rings. IEEE Trans. Selected Areas Comm. 6 (1988) 504-512
    • (1988) IEEE Trans. Selected Areas Comm. , vol.6 , pp. 504-512
    • Taheri, M.1    Jullien, G.A.2    Miller, W.C.3
  • 17
    • 34250890877 scopus 로고
    • On implementing large binary tree architectures in VLSI and WSI
    • Youn H.Y., and Singh A.D. On implementing large binary tree architectures in VLSI and WSI. IEEE Trans. Comput. 38 (1989) 526-537
    • (1989) IEEE Trans. Comput. , vol.38 , pp. 526-537
    • Youn, H.Y.1    Singh, A.D.2
  • 19
    • 0025470947 scopus 로고
    • On modulus replication for residue arithmetic computations of complex inner products
    • Wigley N.M., and Jullien G.A. On modulus replication for residue arithmetic computations of complex inner products. IEEE Trans. Comput. 39 8 (1990) 1065-1076
    • (1990) IEEE Trans. Comput. , vol.39 , Issue.8 , pp. 1065-1076
    • Wigley, N.M.1    Jullien, G.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.