A neural signal detection amplifier with low-frequency noise suppression

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 661-664

  Yoshida, Takeshi ^a   Masui, Yoshihiro ^a   Eki, Ryoji ^a   Iwata, Atsushi ^a   Yoshida, Masayuki ^a   Uematsu, Kazumasa ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

1/F NOISE; AC POWER SUPPLIES; AUTO-ZEROING TECHNIQUES; CMOS TECHNOLOGY; DC OFFSETS; GAIN REDUCTION; INDUCED NOISE; LOW NOISE; LOW POWER; LOW SIGNAL LEVELS; LOW-FREQUENCY NOISE; MIXED SIGNAL; MOSFETS; NEURAL SIGNALS; NEURAL SPIKE; POWER DISSIPATION; SUPPLY NOISE; SUPPLY VOLTAGES; TEST CHIPS; VOLTAGE GAIN;

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; NEURAL NETWORKS; THERMAL NOISE;

SIGNAL DETECTION;

EID: 70350161505     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5117835     Document Type: Conference Paper

References (6)

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6. Reid R.Harrison, "A Low-Power Low-Noise CMOS Amplifier for Neural Recording Applications," IEEE JSSC, VOL.38, NO.6, pp.958-965,June 2003