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Volumn , Issue , 2009, Pages 2886-2889

Implementation of a time-warping AER mapper

Author keywords

[No Author keywords available]

Indexed keywords

ELEMENTARY MOTION DETECTIONS; FPGA BOARDS; NEUROMORPHIC; TEMPORAL CONTRAST;

EID: 70350153868     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5118405     Document Type: Conference Paper
Times cited : (6)

References (18)
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    • Feb-2008
    • P. Lichtsteiner, C. Posch, T. Delbruck, "A 128x128 120dB 15 us Asynchronous Temporal Contrast Vision Sensor". IEEE Journal on Solid-State Circuits, vol. 43, no 2, pp. 566-576, Feb-2008.
    • IEEE Journal on Solid-State Circuits , vol.43 , Issue.2 , pp. 566-576
    • Lichtsteiner, P.1    Posch, C.2    Delbruck, T.3
  • 2
    • 33847616026 scopus 로고    scopus 로고
    • V. Chan, S.C. Liu, A.van Schaik, AER EAR: A Matched Silicon Cochlea Pair with Address-Event-Representation Interface. IEEE TCAS-I. 54, No 1. pp. 48-59. Jan-2007.
    • V. Chan, S.C. Liu, A.van Schaik, "AER EAR: A Matched Silicon Cochlea Pair with Address-Event-Representation Interface". IEEE TCAS-I. Vol. 54, No 1. pp. 48-59. Jan-2007.
  • 4
    • 48949116215 scopus 로고    scopus 로고
    • On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing
    • July-2008
    • R. Serrano-Gotarredona et al. "On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing. IEEE Trans. on Neural Networks, Vol. 19, No 7, pp. 1196-1219. July-2008.
    • IEEE Trans. on Neural Networks , vol.19 , Issue.7 , pp. 1196-1219
    • Serrano-Gotarredona, R.1
  • 5
    • 34047217409 scopus 로고    scopus 로고
    • Adaptive WTA with an Analog VLSI Neuromorphic Learning Chip
    • March
    • P. Hafliger. "Adaptive WTA with an Analog VLSI Neuromorphic Learning Chip". IEEE Transactions on Neural Networks, vol. 18, no 2, pp. 551-572. March-2007.
    • (2007) IEEE Transactions on Neural Networks , vol.18 , Issue.2 , pp. 551-572
    • Hafliger, P.1
  • 6
    • 33244465845 scopus 로고    scopus 로고
    • A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses with Spike-Timig Dependant Plasticity
    • Jan-2006
    • G. Indiveri, E. Chicca, R. Douglas. "A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses with Spike-Timig Dependant Plasticity". IEEE Transactions on Neural Networks, vol. 17, no 1, pp 211-221. Jan-2006.
    • IEEE Transactions on Neural Networks , vol.17 , Issue.1 , pp. 211-221
    • Indiveri, G.1    Chicca, E.2    Douglas, R.3
  • 10
    • 0003609443 scopus 로고
    • Wiring Considerations in analog VLSI Systems with Application to Field-Programmable Networks
    • Ph.D. Thesis, California Institute of Technology, Pasadena CA
    • M. Sivilotti, "Wiring Considerations in analog VLSI Systems with Application to Field-Programmable Networks", Ph.D. Thesis, California Institute of Technology, Pasadena CA, 1991.
    • (1991)
    • Sivilotti, M.1
  • 11
    • 0012532077 scopus 로고    scopus 로고
    • Communicating Neuronal Ensembles between Neuromorphic Chips
    • Kluwer Academic Publishers, Boston
    • K. A. Boahen. "Communicating Neuronal Ensembles between Neuromorphic Chips". Neuromorphic Systems. Kluwer Academic Publishers, Boston 1998.
    • (1998) Neuromorphic Systems
    • Boahen, K.A.1
  • 14
    • 70350197632 scopus 로고    scopus 로고
    • jAER Sourceforge Open Source Project. http://jaer.wiki.sourceforge.net
    • jAER Sourceforge Open Source Project. http://jaer.wiki.sourceforge.net
  • 15
    • 84941516992 scopus 로고
    • Systemtheoretische Analyse der Zeit-, Reihenfolgen-, und Vorzeichenauswertung bei der Bewegungsperzeption des Rüsselkäfers Chlorophanus
    • B. Hassenstein and W. Reichardt. "Systemtheoretische Analyse der Zeit-, Reihenfolgen-, und Vorzeichenauswertung bei der Bewegungsperzeption des Rüsselkäfers Chlorophanus". Z. Naturforch. 11b, pp. 513-524, 1956.
    • (1956) Z. Naturforch , vol.11 b , pp. 513-524
    • Hassenstein, B.1    Reichardt, W.2
  • 16
    • 0034762808 scopus 로고    scopus 로고
    • Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons
    • Jul-2001
    • D.H. Goldberg et al. "Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons". Neural Networks. Vol 14, No 6-7, pp. 781-793. Jul-2001
    • Neural Networks , vol.14 , Issue.6-7 , pp. 781-793
    • Goldberg, D.H.1
  • 17
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    • An Asynchronous 4-to-4 AER Mapper
    • Proc. of IWANN, ISBN 3-540-26208-3
    • H.K. Riis et al. "An Asynchronous 4-to-4 AER Mapper". Proc. of IWANN 2005. LNCS 3512. pp. 494-501. ISBN 3-540-26208-3
    • (2005) LNCS , vol.3512 , pp. 494-501
    • Riis, H.K.1
  • 18
    • 33846098196 scopus 로고    scopus 로고
    • Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses
    • Jan-2007
    • R.J. Vogelstein et al. "Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses". IEEE TNN. Vol. 18, No 1, pp 253-265. Jan-2007
    • IEEE TNN , vol.18 , Issue.1 , pp. 253-265
    • Vogelstein, R.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.