Integrated CMOS resistance-to-period converter with parasitic capacitance evaluation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 1157-1160

  Di Carlo, C ^a   De Marcellis, A ^a   Stornelli, V ^a   Ferri, G ^a   Flammini, A ^b   Depari, A ^b  

^a UNIVERSITY OF L'AQUILA   (Italy)

^b UNIVERSITY OF BRESCIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE BLOCKS; CMOS TECHNOLOGY; EXPERIMENTAL MEASUREMENTS; FREQUENCY RANGES; GAS SENSORS; HIGH DYNAMIC RANGE; INPUT VOLTAGES; INTEGRATED INTERFACE; ON CHIPS; ORDERS OF MAGNITUDE; PARASITIC CAPACITANCE; SLEW-RATE; SYSTEM SENSITIVITY; TRANSISTOR LEVEL;

BANDPASS AMPLIFIERS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; OPERATIONAL AMPLIFIERS;

ANALOG TO DIGITAL CONVERSION;

EID: 70350149875     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5117966     Document Type: Conference Paper

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