-
3
-
-
34548295212
-
Polynomial-time subgraph enumeration for automated instruction set extension
-
P. Bonzini and L. Pozzi. Polynomial-time subgraph enumeration for automated instruction set extension. In DATE '07.
-
DATE '07
-
-
Bonzini, P.1
Pozzi, L.2
-
4
-
-
70350050487
-
Hardware-software codesign for dynamically reconfigurable architectures
-
K. S. Chatha and R. Vemuri. Hardware-software codesign for dynamically reconfigurable architectures. In FPL '99.
-
FPL '99
-
-
Chatha, K.S.1
Vemuri, R.2
-
6
-
-
0032308182
-
CORDS: Hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
-
R. P. Dick and N. K. Jha. CORDS: Hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. In ICCAD '98.
-
ICCAD '98
-
-
Dick, R.P.1
Jha, N.K.2
-
7
-
-
70350072001
-
HiPART: A new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems
-
T. Hollstein, J. Becker, A. Kirschbaum, and M. Glesner. HiPART: A new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. In CODES/CASHE '98.
-
CODES/CASHE '98
-
-
Hollstein, T.1
Becker, J.2
Kirschbaum, A.3
Glesner, M.4
-
8
-
-
34548303541
-
Instruction-set customization for real-time embedded systems
-
H. P. Huynh and T. Mitra. Instruction-set customization for real-time embedded systems. In DATE '07.
-
DATE '07
-
-
Huynh, H.P.1
Mitra, T.2
-
9
-
-
38849103565
-
An efficient framework for dynamic reconfiguration of instruction-set customization
-
H. P. Huynh, J. E. Sim, and T. Mitra. An efficient framework for dynamic reconfiguration of instruction-set customization. In CASES '07.
-
CASES '07
-
-
Huynh, H.P.1
Sim, J.E.2
Mitra, T.3
-
10
-
-
85086611398
-
An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications
-
M. Kaul, R. Vemuri, S. Govindarajan, and I. Ouaiss. An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications. In DAC '99.
-
DAC '99
-
-
Kaul, M.1
Vemuri, R.2
Govindarajan, S.3
Ouaiss, I.4
-
11
-
-
33750902746
-
HW/SW partitioning techniques for multi-mode multi-task embedded applications
-
Y. J. Kim and T. Kim. HW/SW partitioning techniques for multi-mode multi-task embedded applications. In GLSVLSI '06.
-
GLSVLSI '06
-
-
Kim, Y.J.1
Kim, T.2
-
12
-
-
33744962301
-
A hardware-software partitioning and scheduling algorithm for dynamically reconfigurable embedded systems
-
B. Mei, P. Schaumont, and S. Vernalde. A hardware-software partitioning and scheduling algorithm for dynamically reconfigurable embedded systems. In ProRISC '00.
-
ProRISC '00
-
-
Mei, B.1
Schaumont, P.2
Vernalde, S.3
-
13
-
-
0032686439
-
Temporal partitioning and scheduling data flow graphs for reconfigurable computers
-
K. M. G. Purna and D. Bhatia. Temporal partitioning and scheduling data flow graphs for reconfigurable computers. IEEE Transactions on Computers '99.
-
IEEE Transactions on Computers '99
-
-
Purna, K.M.G.1
Bhatia, D.2
-
14
-
-
70350044327
-
Enforcing schedulability of multi-task systems by hardware-software codesign
-
Y. Shin and K. Choi. Enforcing schedulability of multi-task systems by hardware-software codesign. In CODES '97.
-
CODES '97
-
-
Shin, Y.1
Choi, K.2
-
15
-
-
70350077188
-
-
Stretch. S5000 software-configurable processors, 2004.
-
Stretch. S5000 software-configurable processors, 2004.
-
-
-
-
16
-
-
24944546345
-
Scalable custom instruction identification for instruction-set extensible processors
-
P. Yu and T. Mitra. Scalable custom instruction identification for instruction-set extensible processors. In CASES, 2004.
-
(2004)
CASES
-
-
Yu, P.1
Mitra, T.2
|