Mapping for better than worst-case delays in LUT-based FPGA designs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2008, Pages 56-64

  Cong, Jason ^a   Minkovich, Kirill ^a  

^a University of California   (United States)

Author keywords

Better than worst case; FPGA lookup table; Logic synthesis; Razor; Simulation; Switching probabilities; Technology mapping

Indexed keywords

BETTER THAN WORST-CASE; FPGA LOOKUP TABLE; LOGIC SYNTHESIS; RAZOR; SIMULATION; SWITCHING PROBABILITIES; TECHNOLOGY MAPPING;

CONFORMAL MAPPING; DELAY CIRCUITS; DESIGN; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 70349338476     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1344671.1344681     Document Type: Conference Paper

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