A level-crossing analog-to-digital converter with triangular dither

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 9, 2009, Pages 2089-2099

  Wang, Tünde ^a   Wang, Dong ^a   Hurst, Paul J ^a   Levy, Bernard C ^a   Lewis, Stephen H ^a  

^a University of California   (United States)

Author keywords

Analog to digital (A D) conversion; Dither; Interpolation; Level crossing sampling; Nonuniform sampling

Indexed keywords

FREQUENCY CONVERTERS; INTERPOLATION; RAILROAD CROSSINGS;

ANALOG TO DIGITAL CONVERTERS; ANALOG TO DIGITALCONVERSION (A/D); DIGITAL INTERPOLATION; DITHER; LEVEL-CROSSING SAMPLING; NONUNIFORM SAMPLING; ORDER POLYNOMIALS; THRESHOLD LEVELS;

ANALOG TO DIGITAL CONVERSION;

EID: 70349249572     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.2011586     Document Type: Article

References (20)

1. N. Sayiner, H. V. Sorensen, and T. R. Viswanathan, "A new signal acquisition technique," in Proc. 35th Midwest Symp. Circuits Syst. Aug. 1992, vol. 2, pp. 1140-1142.
2. F. Marvasti, Nonuniform Sampling Theory and Practice. New York: Kluwer Academic, 2001.
3. N. Sayiner, H. V. Sorensen, and T. R. Viswanathan, "A non-uniform sampling technique for A/D conversion," in IEEE Int. Symp. Circuits Syst., May 1993, pp. 1220-1223.
4. N. Sayiner, H. V. Sorensen, and T. R. Viswanathan, "A level-crossing sampling scheme for A/D conversion," IEEE Trans. Circuits Syst. II, Anal. Digit. Signal Process., vol. 43, pp. 335-339, Apr. 1996.
5. A. A. Lazar and L. T. Toth, "Perfect recovery and sensitivity analysis of time encoded bandlimited signals," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, pp. 2060-2073, Oct. 2004.
6. E. Allier,G. Sicard, L. Fesquet, and M. Renaudin, "A newclass of asynchronous A/D converters based on time quantization," in Proc. IEEE 9th Int. Symp. Asynchronous Circuits Syst., 2003, pp. 196-205.
7. P. W. Jungwirth and A. D. Poularikas, "Improved Sayiner level crossing ADC," in Proc. 36th Southeastern Symp. Syst. Theory, Mar. 2004, pp. 379-383.
8. B. F. Logan, "Signals designed for recovery after clipping I," AT&T Bell Labs. Tech. J., vol. 63, no. 2, pp. 261-285, Feb. 1984.
9. R. W. Brodersen, P. R. Gray, and D. A. Hodges, "MOS switched-capacitor filters," Proc. IEEE, vol. 67, no. 1, pp. 61-75, Jan. 1979.
10. R. Schaumann, "Continuous-time integrated filters - A tutorial," Proc. IEEE, vol. 136, no. 8, pp. 184-190, Aug. 1989.
11. S. Bernard, F. Azais, Y. Bertrand, and M. Renovell, "A high accuracy triangle-wave signal generator for on-chip ADC testing," in Proc. 7th IEEE Eur. Test Workshop, May 2002, pp. 89-94.
12. J. H. Atherton and H. T. Simmonds, "An offset reduction technique for use with CMOS integrated comparators and amplifiers," IEEE J. Solid-State Circuits, vol. 27, no. 8, pp. 1168-1175, Aug. 1992.
13. T. Shih, L. Der, S. H. Lewis, and P. J. Hurst, "A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection," IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 250-253, Feb. 1997.
14. Y. W. Li, K. L. Shepard, and Y. P. Tsividis, "Continuous-time digital signal processors," in Proc. 11th IEEE Int. Symp. Asynchronous Circuits Syst., Mar. 2005, pp. 138-143.
15. F. Aeschlimann, E. Allier, L. Fesquet, and M. Renaudin, "Asynchronous FIR filters: Towards a new digital processing chain," in Proc. 10th Int. Symp. Asynchronous Circuits Syst., 2004, pp. 198-206.
16. M. Unser, "Splines," IEEE Signal Process. Mag., pp. 22-38, Nov. 1999.
17. H. Choi and R. Baraniuk, "Interpolation and denoising of non-uniformly sampled data using wavelet-domain processing," in Int. Conf. Acoust., Speech, Signal Process., 1999, pp. 1645-1648.
18. R. L. Burden and J. D. Faires, Numerical Analysis. Pacific Grove, CA: Brooks/Cole, 2001.
19. Q. Zhang, "Some implementation aspects of sliding window least squares algorithms," in Proc. 12th IFAC Symp. Syst. Identification, 2001, vol. 2, pp. 763-768.
20. G. Strang, Introduction to Linear Algebra. Wellesley, MA: Wellesley-Cambridge Press, 1993.