The challenges of petascale architectures

Computing in Science and Engineering

Volumn 11, Issue 5, 2009, Pages 10-16

  Kogge, Peter M ^a  

^a UNIVERSITY OF NOTRE DAME   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PETAFLOPS; PETASCALE; TERASCALE;

EID: 70349204142     PISSN: 15219615     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCSE.2009.150     Document Type: Article

References (8)

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2. T. Sterling, P. Messina, and P. Smith, Enabling Technologies for Petaflops Computing, MIT Press, 1995.
3. G. Gao et al., "Hybrid Technology Multithreaded Architecture," Proc. 6th Symp. Frontiers of Massively Parallel Computation, IEEE CS Press, 1996, pp. 98-105.
4. J. Kepner, "HPC Productivity: An Overarching View," Int'l J. High Performance Computing Applications, vol.18, no.4, 2004, pp. 393-397.
5. P. Kogge, "The Execube Approach to Massively Parallel Processing," Proc. Int'l Conf. Parallel Processing (ICPP 94), CRC Press, 1994, pp. 77-84.
6. A. Bright et al., "Creating the BlueGene/L Supercomputer from Low-Power SoC ASICs," IEEE Int'l Solid State Circuits Conf. (ISSCC 05), IEEE CS Press, 2005, pp. 188-189.
7. J. Kahle et al., "Introduction to the Cell Multiprocessor," IBM J. Research and Development, vol.49, nos. 4-5, 2005, pp. 589-604.
8. P. Kogge et al., "ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems," Sept. 2008; www.cse.nd.edu/Reports/2008/ TR-2008-13.pdf.