FPGA-optimized GNSS receiver implementation techniques

21st International Technical Meeting of the Satellite Division of the Institute of Navigation, ION GNSS 2008

Volumn 2, Issue , 2008, Pages 1210-1215

  Cobb, H Stewart ^a  

^a Novariant Inc

Author keywords

[No Author keywords available]

Indexed keywords

CORDIC ALGORITHMS; DUAL-PORT MEMORIES; FPGA IMPLEMENTATIONS; GNSS RECEIVERS; HIGH-SPEED SERIAL; LOW COSTS; MASS PRODUCTION; OPEN MARKET; RESEARCH PROGRAMS; SMALL-VOLUME PRODUCTION; TIME-SHARING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; GLOBAL POSITIONING SYSTEM; INDUSTRIAL RESEARCH; INTEGRATED CIRCUITS; NAVIGATION; SHIFT REGISTERS; SIGNAL PROCESSING; SIGNAL RECEIVERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 69949189171     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Andraka, Ray. A Survey of CORDIC Algorithms for FPGA Based Computers. ACM FPGA-98 conference, Monterey, California. 1998.
2. Andraka, Ray. Building a High-Performance Bit-Serial Processor in an FPGA. Design SuperCon 1996 conference, Santa Clara, California. 1996.
3. Bresenham, Jack. Algorithm for Computer Control of a Digital Plotter. IBM Systems Journal, 4(1):25-30, 1965
4. Walther, J.S. A Unified Algorithm for Elementary Functions. Spring 1971 Joint Computer Conference, Proc. pp. 379-385. 1971.
5. Volder, Jack. The CORDIC Trigonometric Computing Technique. IRE Transactions on Electronic Computers, Vol.EC-8, No.3, pp. 330-334. 1959.
6. Xilinx. Spartan-3 Generation FPGA User Guide, version 1.4, June 25, 2008.