Design verification for sub 70 nm DRAM nodes via metal fix using E-beam direct write

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7470, Issue , 2009, Pages

  Keil, K ^a   Jaschinsky, P ^a   Hohle, C ^b   Choi, K H ^b   Schneider, R ^b   Tesauro, M ^b   Thrum, F ^b   Zimmermann, R ^b   Kretz, J ^b  

^a Fraunhofer Center Nanoelectronic Technologies   (Germany)

^b QIMONDA DRESDEN GMBH AND CO OHG   (Germany)

Author keywords

Design verification; E beam lithography; EBDW; Metal fix; Mix match

Indexed keywords

ALIGNMENT MARKS; CHIP PROCESSING; DESIGN VERIFICATION; DIRECT WRITE; E-BEAM LITHOGRAPHY; EBDW; ELECTRICAL DEVICES; ELECTRON BEAM DIRECT WRITE; FLEXIBLE DESIGNS; HARDMASKS; IS DESIGN; LARGE CHIPS; LITHO PROCESS; MASK COST; METAL LAYER; SEMICONDUCTOR INDUSTRY; SMALL-VOLUME PRODUCTION; SPECIAL APPLICATIONS; SUB-70NM;

ALIGNMENT; CONCURRENT ENGINEERING; DYNAMIC RANDOM ACCESS STORAGE; ELECTRON BEAMS; JOB ANALYSIS; METAL CUTTING; METALS; RAPID PROTOTYPING; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS; SOFTWARE PROTOTYPING;

ELECTRON BEAM LITHOGRAPHY;

EID: 69949178860     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.835206     Document Type: Conference Paper

References (3)

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