Hardness assurance test guideline for qualifying devices for use in proton environments

IEEE Transactions on Nuclear Science

Volumn 56, Issue 4, 2009, Pages 2171-2178

  Schwank, J R ^a   Shaneyfelt, M R ^a   Dodd, P E ^a   Felix, J A ^a   Baggio, J ^b   Ferlet Cavrois, V ^b   Paillet, P ^b   Label, K A ^c   Pease, R L ^d   Simons, M ^e   Cohn, L M ^f  

^a SANDIA NATIONAL LABORATORIES   (United States)

^b CEA DIF   (France)

^c NASA HEADQUARTERS   (United States)

^d RLP Research   (United States)

^e RTI INTERNATIONAL   (United States)

^f DTRA   (United States)

Author keywords

Integrated circuit reliability; Integrated circuit testing; Proton testing; Radiation effects; Radiation hardening (electronics); Radiation response; Single event effects; Single event latchup; Single event upset

Indexed keywords

INTEGRATED CIRCUIT RELIABILITY; PROTON TESTING; RADIATION HARDENING (ELECTRONICS); RADIATION RESPONSE; SINGLE EVENT EFFECTS; SINGLE EVENT LATCHUP; SINGLE EVENT UPSET;

DATA COMPRESSION; ELECTRIC NETWORK ANALYSIS; FLASH MEMORY; HARDENING; HARDNESS; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; IONIZING RADIATION; PROTONS; RADIATION HARDENING; STATIC RANDOM ACCESS STORAGE; URANIUM POWDER METALLURGY;

RADIATION EFFECTS;

EID: 69549134250     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2009.2013239     Document Type: Conference Paper

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