Modeling and verification of real-time embedded systems with urgency

Journal of Systems and Software

Volumn 82, Issue 10, 2009, Pages 1627-1641

  Hsiung, Pao Ann ^a   Lin, Shang Wei ^a   Chen, Yean Ru ^b   Huang, Chun Hsian ^a   Shih, Chihhsiong ^c   Chu, William C ^c  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c TUNGHAI UNIVERSITY   (Taiwan)

Author keywords

Formal verification; Modeling; Urgency

Indexed keywords

CTL MODEL; FORMAL VERIFICATION; MODEL CHECK; MODEL CHECKER; MODELING; REAL-TIME AND EMBEDDED SYSTEMS; REAL-TIME EMBEDDED SYSTEMS; STATE SPACE; SUFFICIENT CONDITIONS; SYSTEM STATE; TIMED AUTOMATA; TIMED AUTOMATA MODELS; TOOLSETS; URGENCY; VERIFICATION METHOD; ZONE PARTITIONING; ZONE-BASED;

EMBEDDED SYSTEMS; MARKUP LANGUAGES; REAL TIME SYSTEMS; ROBOTS; SEMANTICS; TRANSLATION (LANGUAGES);

MODEL CHECKING;

EID: 69549112903     PISSN: 01641212     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jss.2009.03.013     Document Type: Article

References (25)

1. Alur R., and Dill D.L. A theory of timed automata. Theoretical Computer Science 126 2 (1994) 183-235
2. Alur, R., Courcoubetis, C., Dill, D.L., 1990. Model-checking for real-time systems. In: Proceedings of the 5th Annual Symposium on Logic in Computer Science, IEEE Computer Society Press, pp. 414-425.
3. Barbuti R., and Tesei L. Timed automata with urgent transitions. Acta Informatica 40 5 (2004) 317-347
4. Bengtsson, J., Larsen, K., Larsson, F., Pettersson, P., Wang, Y., 1995. UPPAAL: a tool suite for automatic verification of real-time systems. In: Proceedings of Workshop on Verification and Control of Hybrid Systems III, LNCS, vol. 1066, pp. 232-243.
5. Bornot S., and Sifakis J. An algebraic framework for urgency. Information and Computation 163 1 (2000) 172-202
6. Bornot, S., Sifakis, J., Tripakis, S., 1997. Modeling urgency in timed systems. In: Proceedings of the International Symposium on Compositionality: The Significant Difference, LNCS, vol. 1536, Springer-Verlag, pp. 103-129.
7. Bowman, H., Faconti, G., Katoen, J.-P., Latella, D., Massink, M., 1998. Automatic verification of a lip synchronisation algorithm using UPPAAL. In: Proceedings of the 3rd International Workshop on Formal Methods for Industrial Critical Systems, pp. 97-124.
8. Bozga, M., Fernandez, J.Cl., Ghirvu, L., Graf, S., Krimm, J.P., Mounier, L., 1999. IF: an intermediate representation and validation environment for time asynchronous systems. In: Proceedings of the Formal Methods Conference (FM), September 1999, pp. 307-327.
9. Bozga, M., Graf, S., Mounier, L., Ober, I., Roux, J.-L., Vincent, D., 2001. Timed extensions for SDL. In: Proceedings of the 10th SDL Forum, LNCS, vol. 2078, Springer-Verlag, pp. 223-240.
10. Cassez, F., Pagetti, C., Roux, O., 2002. A timed extension for AltaRica. Research Report R 12002-13, IRCCyN/CNRS, Nantes, France. .
11. Clarke E.M., Emerson. E.A., 1981. Design and sythesis of synchronization skeletons using branching time temporal logic. In: Proceedings of the Logics of Programs Workshop, LNCS, vol. 131, Springer-Verlag, pp. 52-71.
12. Dill, D.L., 1989. Timing assumptions and verification of finite-state concurrent systems. In: Proceedings of Workshop on Automatic Verification Methods for Finite State Systems, LNCS, vol. 407, Springer-Verlag, pp. 197-212.
13. Gebremichael, B., Vaandrager, F., 2005. Specifying urgency in timed I/O automata. In: Proceedings of the 3rd IEEE International Conference on Software Engineering and Formal Methods (SEFM), pp. 5-9.
14. Henzinger, T.A., Nicollin, X., Sifakis, J., Yovine, S., 1992. Symbolic model checking for real-time systems. In: Proceedings of the IEEE International Conference on Logics in Computer Science (LICS), pp. 394-406.
15. Hogrefe, D., Koch, B., Neukirchen, H., Some implications of MSC, SDL, and TTCN timed extensions for computer aided test generation. In: Proceedings of the 10th SDL Forum, LNCS, vol. 2078, Springer-Verlag, pp. 168-181.
16. Hsiung, P.-A., Wang. F., 1998. A state-graph manipulator tool for real-time system specification and verification. In: Proceedings of the 5th International Conference on Real-Time Computing Systems and Applications (RTCSA).
17. INTERVAL Consortium, 1999-2001. Interval project: formal design, validation and testing of real-time telecommunication systems, (definition of the timed extensions to SDL, MSC, TTCN). IST-1999-11557. .
18. Kaynar, D.K., Lynch, N., Segala, R., Vaandrager, F., 2003. Timed I/O automata: a mathematical framework for modeling and analyzing real-time systems. In: Proceedings of the 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, pp. 166-177.
19. Kwiatkowska, M., Norman, G., Segala, R., Sproston, J., 2000. Verifying soft deadlines with probablistic timed automata. In: Proceedings of the Workshop on Advances in Verification (WAVe).
20. Lin, S.-W., Hsiung, P.-A., Huang, C.-H., Chen, Y.-R., 2005. Model checking prioritized timed automata. In: Proceedings of the 3rd International Symposium on Automated Technology for Verification and Analysis (ATVA), LNCS, vol. 3707, Springer-Verlag, pp. 370-384.
21. Sifakis, J., Yovine, S., 1996. Compositional specification of timed systems. In: Proceedings of the 13th Annual Symposium on Theoretical Aspects of Computer Science (STACS), LNCS, vol. 1046, Springer-Verlag, pp. 347-359.
22. Stefani J.-B., Hazard L., and Horn F. Computational model for distributed multimedia application based on a synchronous programming language. Computer Communications (Special Issue on FDTs) 15 2 (1992) 114-128
23. Wang, F., 2001. RED: model-checker for timed automata with clock-restriction diagram. In: Proceedings of the Workshop on Real-Time Tools, August 2001, Technical Report 2001-014, Department of Information Technology, Uppsala University, ISSN:1404-3203.
24. Wang F., and Hsiung P.-A. Efficient and user-friendly verification. IEEE Transactions on Computers 51 1 (2002) 61-83
25. Yovine S. Kronos: a verification tool for real-time systems. International Journal of Software Tools for Technology Transfer 1 1/2 (1997) 123-133