-
1
-
-
77957958942
-
A new class of asynchronous A/D converters based on time quantization
-
E. Allier, G. Sicard, L. Fesquet, and M. Renaudin, "A new class of asynchronous A/D converters based on time quantization," in Proc. 9th Int. Symp. Asynchronous Circuits Syst., 2003, pp. 196-205.
-
(2003)
Proc. 9th Int. Symp. Asynchronous Circuits Syst
, pp. 196-205
-
-
Allier, E.1
Sicard, G.2
Fesquet, L.3
Renaudin, M.4
-
2
-
-
0030128754
-
A level-crossing sampling scheme for A/D conversion
-
Apr
-
N. Sayiner, H. Sorensen, and T. Viswanathan, "A level-crossing sampling scheme for A/D conversion," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 4, pp. 335-339, Apr. 1996.
-
(1996)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.43
, Issue.4
, pp. 335-339
-
-
Sayiner, N.1
Sorensen, H.2
Viswanathan, T.3
-
4
-
-
69449088837
-
A low propagation delay dispersion comparator for a level-crossing AD converter, Analog Integr. Circuits Signal Process. [Online]. Available: http://www.springerlink.com/content/1003812741m01m32/ ?p=697b1c4d60fc46f887ee9ec497cc534ep=8
-
to be published
-
K. Kozmin, J. Johansson, and J. Kostamovaara, "A low propagation delay dispersion comparator for a level-crossing AD converter," Analog Integr. Circuits Signal Process. [Online]. Available: http://www.springerlink.com/content/1003812741m01m32/ ?p=697b1c4d60fc46f887ee9ec497cc534ep=8, to be published
-
-
-
Kozmin, K.1
Johansson, J.2
Kostamovaara, J.3
-
5
-
-
33746623994
-
A CMOS time-to-digital converter with better than 10 ps single-shot precision
-
Jun
-
J.-P. Jansson, A. Mantyniemi, and J. Kostamovaara, "A CMOS time-to-digital converter with better than 10 ps single-shot precision," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1286-1296, Jun. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.6
, pp. 1286-1296
-
-
Jansson, J.-P.1
Mantyniemi, A.2
Kostamovaara, J.3
-
6
-
-
69449098996
-
-
P. Ferreira and J. Benedetto, Eds, Cambridge, MA: Birkhäuser, ch. 1.2, pp
-
P. Ferreira and J. Benedetto, Eds., Modern Sampling Theory. Cambridge, MA: Birkhäuser, 2001, ch. 1.2, pp. 10-11.
-
(2001)
Modern Sampling Theory
, pp. 10-11
-
-
-
7
-
-
0006943989
-
Efficient methods for digital signal and image reconstruction from nonuniform samples,
-
Ph.D. dissertation, Institut für Matehematik der Universitäat Wien, Wien, Austria
-
T. Strohmer, "Efficient methods for digital signal and image reconstruction from nonuniform samples," Ph.D. dissertation, Institut für Matehematik der Universitäat Wien, Wien, Austria, 1993.
-
(1993)
-
-
Strohmer, T.1
-
8
-
-
21844510105
-
Efficient numerical methods in non-uniform sampling theory
-
Feb, Online, Available
-
H. G. Feichtinger, K. Gröchenig, and T. Strohmer, "Efficient numerical methods in non-uniform sampling theory," Numer. Math. vol. 69, no. 4, pp. 423-440, Feb. 1995 [Online]. Available: citeseer.ist.psu.edu/article/feichtinger95efficient.html
-
(1995)
Numer. Math
, vol.69
, Issue.4
, pp. 423-440
-
-
Feichtinger, H.G.1
Gröchenig, K.2
Strohmer, T.3
-
9
-
-
34548820213
-
Analysis of continuous-time digital signal processors
-
May
-
B. Schell and Y. Tsividis, "Analysis of continuous-time digital signal processors," in Proc. IEEE ISCAS, May 2007, pp. 2232-2235.
-
(2007)
Proc. IEEE ISCAS
, pp. 2232-2235
-
-
Schell, B.1
Tsividis, Y.2
-
10
-
-
46749136514
-
Nonuniform sampling of periodic bandlimited signals
-
Jul
-
E. Margolis and Y. Eldar, "Nonuniform sampling of periodic bandlimited signals," IEEE Trans. Signal Process., vol. 56, no. 7, pp. 2728-2745, Jul. 2008.
-
(2008)
IEEE Trans. Signal Process
, vol.56
, Issue.7
, pp. 2728-2745
-
-
Margolis, E.1
Eldar, Y.2
-
11
-
-
54749086413
-
Reconstruction of nonuniformly sampled bandlimited signals using a differentiator-multiplier cascade
-
Sep
-
S. Tertinek and C. Vogel, "Reconstruction of nonuniformly sampled bandlimited signals using a differentiator-multiplier cascade," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 8, pp. 2273-2286, Sep. 2008.
-
(2008)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.55
, Issue.8
, pp. 2273-2286
-
-
Tertinek, S.1
Vogel, C.2
-
12
-
-
69449105145
-
On the estimation of the bandwidth of nonuniformly sampled signals
-
Mar
-
T. Strohmer, "On the estimation of the bandwidth of nonuniformly sampled signals," in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., Mar. 1999, vol. 4, pp. 2047-2050.
-
(1999)
Proc. IEEE Int. Conf. Acoust., Speech, Signal Process
, vol.4
, pp. 2047-2050
-
-
Strohmer, T.1
-
13
-
-
0024088514
-
Nonlinear ADC with digitally selectable quantizing characteristic
-
Oct
-
J. Lygouras, "Nonlinear ADC with digitally selectable quantizing characteristic," IEEE Trans. Nucl. Sci., vol. 35, no. 5, pp. 1088-1091, Oct. 1988.
-
(1988)
IEEE Trans. Nucl. Sci
, vol.35
, Issue.5
, pp. 1088-1091
-
-
Lygouras, J.1
-
14
-
-
34547332842
-
CMOS image sensor with analog gamma correction using nonlinear single-slope ADC
-
May 21-24
-
S. Ham, Y. Lee, W. Jung, S. Lim, K. Yoo, Y. Chae, J. Cho, D. Lee, and G. Han, "CMOS image sensor with analog gamma correction using nonlinear single-slope ADC," in Proc. IEEE Int. Symp. Circuits Syst., May 21-24, 2006, pp. 3578-3581.
-
(2006)
Proc. IEEE Int. Symp. Circuits Syst
, pp. 3578-3581
-
-
Ham, S.1
Lee, Y.2
Jung, W.3
Lim, S.4
Yoo, K.5
Chae, Y.6
Cho, J.7
Lee, D.8
Han, G.9
-
16
-
-
35348934440
-
A low power multi-channel single ramp ADC with up to 3.2 GHz virtual clock
-
Oct
-
E. Delagnes, D. Breton, F. Lugiez, and R. Rahmanifard, "A low power multi-channel single ramp ADC with up to 3.2 GHz virtual clock," IEEE Trans. Nucl. Sci., vol. 54, no. 5, pp. 1735-1742, Oct. 2007.
-
(2007)
IEEE Trans. Nucl. Sci
, vol.54
, Issue.5
, pp. 1735-1742
-
-
Delagnes, E.1
Breton, D.2
Lugiez, F.3
Rahmanifard, R.4
-
17
-
-
48349136346
-
A fast integrating ADCusing precise time-to-digital conversion
-
Oct. 26-Nov. 3
-
T. Fusayasu, "A fast integrating ADCusing precise time-to-digital conversion," in Proc. IEEE NSS, Oct. 26-Nov. 3 2007, vol. 1, pp. 302-304.
-
(2007)
Proc. IEEE NSS
, vol.1
, pp. 302-304
-
-
Fusayasu, T.1
-
19
-
-
46749156902
-
A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion
-
Jul
-
S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, and D. Schmitt-Landsiedel, "A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion," IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1666-1676, Jul. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.7
, pp. 1666-1676
-
-
Henzler, S.1
Koeppe, S.2
Lorenz, D.3
Kamp, W.4
Kuenemund, R.5
Schmitt-Landsiedel, D.6
-
20
-
-
41549133070
-
A 9 b, 1.25 ps resolution coarse-fine time-todigital converter in 90 nm CMOS that amplifies a time residue
-
Apr
-
M. Lee and A. Abidi, "A 9 b, 1.25 ps resolution coarse-fine time-todigital converter in 90 nm CMOS that amplifies a time residue," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769-777, Apr. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.4
, pp. 769-777
-
-
Lee, M.1
Abidi, A.2
-
21
-
-
33645827149
-
Receiver channel with resonance-based timing detection for a laser range finder
-
Mar
-
J. Pehkonen, P. Palojärvi, and J. Kostamovaara, "Receiver channel with resonance-based timing detection for a laser range finder," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp. 569-577, Mar. 2006.
-
(2006)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.53
, Issue.3
, pp. 569-577
-
-
Pehkonen, J.1
Palojärvi, P.2
Kostamovaara, J.3
-
22
-
-
33645669128
-
A 14-bit digitally selfcalibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s
-
Apr
-
K. Iizuka, H. Matsui, M. Ueda, and M. Daito, "A 14-bit digitally selfcalibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 883-890, Apr. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.4
, pp. 883-890
-
-
Iizuka, K.1
Matsui, H.2
Ueda, M.3
Daito, M.4
-
23
-
-
33746874490
-
A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 db SFDR and 50 fs jitter
-
Aug
-
A. Ali, C. Dillon, R. Sneed, A. Morgan, S. Bardsley, J. Kornblum, and L. Wu, "A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 db SFDR and 50 fs jitter," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1846-1855, Aug. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.8
, pp. 1846-1855
-
-
Ali, A.1
Dillon, C.2
Sneed, R.3
Morgan, A.4
Bardsley, S.5
Kornblum, J.6
Wu, L.7
-
24
-
-
33845804814
-
An ultra-energy-efficient wide-bandwidth video pipeline ADC using optimized architectural partitioning
-
Dec
-
O. A. Adeniran and A. Demosthenous, "An ultra-energy-efficient wide-bandwidth video pipeline ADC using optimized architectural partitioning," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2485-2497, Dec. 2006.
-
(2006)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.53
, Issue.12
, pp. 2485-2497
-
-
Adeniran, O.A.1
Demosthenous, A.2
-
25
-
-
33847752977
-
A 10-bit 50-MS/s pipelined ADC with opamp current reuse
-
Mar
-
S. Ryu, B. Song, and K. Bacrania, "A 10-bit 50-MS/s pipelined ADC with opamp current reuse," IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 475-485, Mar. 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.3
, pp. 475-485
-
-
Ryu, S.1
Song, B.2
Bacrania, K.3
-
26
-
-
57849140436
-
A 10-bit 205-MS/s 1.0-mm 90-nm CMOS pipeline ADC for flat panel display applications
-
Dec
-
S.-C. Lee, Y.-D. Jeon, J.-K. Kwon, and J. Kim, "A 10-bit 205-MS/s 1.0-mm 90-nm CMOS pipeline ADC for flat panel display applications," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2688-2695, Dec. 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.12
, pp. 2688-2695
-
-
Lee, S.-C.1
Jeon, Y.-D.2
Kwon, J.-K.3
Kim, J.4
-
27
-
-
27644434775
-
An 11b 70-MHz 1.2- mm 49-mW 0.18-μm CMOSADC with on-chip current/voltage references
-
Oct
-
Y.-J. Cho and S.-H. Lee, "An 11b 70-MHz 1.2- mm 49-mW 0.18-μm CMOSADC with on-chip current/voltage references," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 10, pp. 1989-1995, Oct. 2005.
-
(2005)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.52
, Issue.10
, pp. 1989-1995
-
-
Cho, Y.-J.1
Lee, S.-H.2
-
28
-
-
2442692681
-
A 6 b 600 MHz 10 mW ADC array in digital 90 nm CMOS
-
Feb. 15-19
-
D. Draxelmayr, "A 6 b 600 MHz 10 mW ADC array in digital 90 nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 15-19, 2004, vol. 1, pp. 264-527.
-
(2004)
Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers
, vol.1
, pp. 264-527
-
-
Draxelmayr, D.1
|