Implementing a digitally synthesized adaptive pre-emphasis algorithm for use in a high-speed backplane interconnection

Canadian Conference on Electrical and Computer Engineering

Volumn 3, Issue , 2004, Pages 1221-1224

  Lin, Lei ^a   Noel, Peter ^a   Kwasniewski, Tad ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

Adaptive pre emphasis; Digital asic; Multi level pam

Indexed keywords

HIGH-SPEED TRANSMISSION; PRE-EMPHASIS; SKIN EFFECTS;

ADAPTIVE ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; COMPUTER SIMULATION; DIELECTRIC LOSSES; ERROR ANALYSIS; NATURAL FREQUENCIES; PULSE AMPLITUDE MODULATION; TRANSCEIVERS; VLSI CIRCUITS;

INTERCONNECTION NETWORKS;

EID: 6944221899     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Stonick, et.al., "An Adaptive PAM-4 5-Gb/s Backplane Transceiver in 0.25-μm CMOS", IEEE J. Solid-State Circuits, vol. 38, pp 436-443, March 2003.
2. S. Haykin, "Adaptive Filter Theory", third edition, Prentice Hall, New Jersey, 1996.
3. R. Farjad-Rad, et.al., "A 0.3-μm CMOS 8-Gb/s 4-PAM Serial Link Transceiver", IEEE. J. Solid-State Circuits, vol. 35, pp. 757-764, May 2000.