Cross-abstraction functional verification and performance analysis of chip multiprocessor designs

IEEE Transactions on Industrial Informatics

Volumn 5, Issue 3, 2009, Pages 241-256

  Madl, Gabor ^a   Pasricha, Sudeep ^b   Dutt, Nikil ^a   Abdelwahed, Sherif ^c  

^a Irvine   (United States)

^b Department of Environmental and Radiological Health Sciences   (United States)

^c MISSISSIPPI STATE UNIVERSITY   (United States)

Author keywords

Bus matrix interconnect; Chip multiprocessor (CMP); Model checking; Performance analysis; Real time

Indexed keywords

ACCURACY LOSS; CHIP MULTIPROCESSOR; CHIP MULTIPROCESSOR (CMP); CROSSBAR SWITCH; CYCLE ACCURATE; DISCRETE EVENTS; DOMAIN-SPECIFIC MODELING LANGUAGE; FINITE STATE MACHINES; FORMAL PROPERTIES; FUNCTIONAL VERIFICATION; INDUSTRIAL STRENGTH; INHERENT COMPLEXITY; MATRIX; MODEL CHECKER; MODEL-BASED; MODEL-BASED TOOLS; MODELS OF COMPUTATION; MULTIPLE MODELS; OPEN SOURCE TOOLS; PERFORMANCE ANALYSIS; PERFORMANCE ESTIMATION; REAL TIME ANALYSIS; REAL-TIME; TIMED AUTOMATA MODELS;

ABSTRACTING; BUSES; DESIGN; ESTIMATION; INTERCONNECTION NETWORKS; MATRIX ALGEBRA; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; SWITCHING CIRCUITS; SYSTEMS ANALYSIS; TELECOMMUNICATION NETWORKS;

MODEL CHECKING;

EID: 69249210879     PISSN: 15513203     EISSN: None     Source Type: Journal    
DOI: 10.1109/TII.2009.2026896     Document Type: Article

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