Impact of on-chip network parameters on NUCA cache performances

IET Computers and Digital Techniques

Volumn 3, Issue 5, 2009, Pages 501-512

  Bardine, A ^a   Comparetti, M ^a   Foglia, P ^a   Gabrielli, G ^a   Prete, C A ^a  

^a UNIVERSITY OF PISA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS LATENCY; AVERAGE NUMBER OF HOPS; BUFFERING CAPACITIES; CACHE ACCESS; CACHE CONTROLLER; CACHE PERFORMANCE; CUT-THROUGH; CYCLE ACCURATE; ENTIRE SYSTEM; EXECUTION-DRIVEN SIMULATORS; HYBRID NETWORK; LATENCY INCREASE; LATENCY REDUCTION; NETWORK ELEMENT; NETWORK ROUTERS; NON-UNIFORM CACHE ARCHITECTURE; NOVEL DESIGN; ON-CHIP CACHE; ON-CHIP NETWORKS; PERFORMANCE LEVEL; SINGLE PROCESSORS; SWITCHED NETWORKS; WORK ANALYSIS;

ELECTRIC NETWORK TOPOLOGY; SWITCHING CIRCUITS;

ROUTERS;

EID: 68849097069     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2008.0078     Document Type: Article

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