Low-power programmable FPGA routing circuitry

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 8, 2009, Pages 1048-1060

  Anderson, Jason H ^a   Najm, Farid N ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Field programmable gate arrays (FPGAs); Interconnect; Leakage; Optimization; Power

Indexed keywords

CIRCUIT TECHNIQUES; DIFFERENT MODES; DYNAMIC POWER; FIELD-PROGRAMMABLE GATE ARRAYS (FPGAS); FPGA DESIGN; HIGH-SPEED; INTERCONNECT; LEAKAGE; LEAKAGE POWER; LOW POWER; LOW-POWER MODE; OVERALL DESIGN; POWER; POWER CONSUMPTION; PROGRAMMABLE GATE ARRAY; ROUTING SWITCHES; SLEEP MODE; SMALL AREA; SWITCH DESIGNS; TIMING SLACK;

DESIGN; ELECTRIC POWER UTILIZATION; ELECTRIC SWITCHES; LOGIC GATES; SPEED;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 68549135002     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2017443     Document Type: Article

References (34)

1. ITRS, quot;International Technology Roadmap for Semiconductors,quot; 2002 [Online]. Available: http://www.itrs.org
2. V. George and J. Rabaey, Low-Energy FPGAs: Architecture and Design. Boston, MA: Kluwer, 2001.
3. I. Kuon and J. Rose, quot;Measuring the gap between FPGAs and ASICs,quot; IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 2, pp. 203-215, Feb. 2007.
4. L. Shang, A. Kaviani, and K. Bathala, quot;Dynamic power consumption in the Virtex-II FPGA family,quot; in Proc. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, Monterey, CA, 2002, pp. 157-164.
5. T. Tuan and B. Lai, quot;Leakage power analysis of a 90 nm FPGA,quot; in Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, 2003, pp. 57-60.
6. F. Li, D. Chen, L. He, and J. Cong, quot;Architecture evaluation for power-efficient FPGAs,quot; in Proc. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, Monterey, CA, 2003, pp. 175-184.
7. A. Rahman and V. Polavarapuv, quot;Evaluation of low-leakage design techniques for field-programmable gate arrays,quot; in Proc. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, Monterey, CA, 2004, pp. 23-30.
8. K. Poon, A. Yan, and S. J. E. Wilton, quot;A flexible power model for FPGAs,quot; in Proc. Int. Conf. Field-Program. Logic Appl., Montpellier, France, 2002, pp. 312-321.
9. Actel, Corp., Mountain View, CA, quot;IGLOO low-power flash FPGAs general description,quot; 2007.
10. Xilinx, Inc., San Jose, CA, quot;Spartan-3 FPGA data sheet,quot; 2004.
11. J. Anderson and F. Najm, quot;A novel low-power FPGA routing switch,quot; in Proc. IEEE Custom Integr. Circuits Conf., Orlando, FL, 2004, pp. 719-722.
12. J. Anderson and F. Najm, quot;Low-power programmable FPGA routing circuitry,quot; in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, 2004, pp. 602-609.
13. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, quot;Leakage current mechanisms and leakage reduction techniques in deep-submi-crometer CMOS circuits,quot;Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
14. M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, quot;Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique,quot; in Proc. ACM/IEEE Des. Autom. Conf., New Orleans, LA, 2002, pp. 480-485.
15. K. Kumagai, H. Iwaki, H. Yoshida, H.Suzuki, T. Yamada, and S. Kurosawa, quot;A novel powering-down scheme for low Vt CMOS circuits,quot; in Proc. IEEE Symp. VLSI Circuits, Honolulu, HI, 1998, pp. 44-45.
16. R. Krishnamurthy, A. Alvandpour, V. De, and S. Borkar, quot;High-performance and low-power challenges for sub-70 nm microprocessor circuits,quot; in Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, 2002, pp. 125-128.
17. D. Lewis, V. Betz, D. Jefferson, A. Lee, C. Lane, P. Leventis, S. Mar-quardt, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki, R. Cliff, and J. Rose, quot;The Stratix routing and logic architecture,quot; in Proc. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, Monterey, CA, 2003, pp. 12-20.
18. G. Lemieux, quot;Routing architecture for field-programmable gate arrays,quot; Ph.D. dissertation, Dept. Electr. Comput. Eng., Univ. Toronto, Toronto, ON, Canada, 2003.
19. F. Li, Y. Lin, L. He, and J. Cong, quot;Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics,quot; in Proc. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, Monterey, CA, 2004, pp. 42-50.
20. F. Li, Y. Lin, and L. He, quot;FPGA power reduction using configurable dual-Vdd,quot; in Proc. ACM/IEEE Des. Autom. Conf., San Diego, CA, 2004, pp. 735-740.
21. A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. Irwin, and T. Tuan, quot;A dual-Vdd low power FPGA architecture,quot; in Proc. Int. Conf. Field-Programmable Logic Appl., Antwerp, Belgium, 2004, pp. 145-157.
22. F. Li and L. He, quot;Vdd programmability to reduce FPGA interconnect power,quot; in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, 2004, pp. 760-765.
23. B. Calhoun, F. Honore, and A. Chandrakasan, quot;Design methodology for fine-grained leakage control in MTCMOS,quot; in Proc. ACM/IEEE Int. Symp. Low-Power Electron. Des., Seoul, Korea, 2003, pp. 104-109.
24. A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. Irwin, and T. Tuan, quot;Reducing leakage energy in FPGAs using region-constrained placement,quot; in Proc. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, Monterey, CA, 2004, pp. 51-58.
25. L. Ciccarelli, A. Lodi, and R. Canegallo, quot;Low leakage circuit design for FPGAs,quot; in Proc. IEEE Custom Integr. Circuits Conf., Orlando, FL, 2004, pp. 715-718.
26. Q. Wang and S. B. K. Vrudhula, quot;Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits,quot; IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 3, pp. 306-318, Mar. 2002.
27. V. Betz, quot;Architecture and CAD for the speed and area optimization of FPGAs,quot; Ph.D. dissertation, Dept. Electr. Comput. Eng., Univ. Toronto, Toronto, ON, Canada, 1998.
28. M. Hutton, V. Chan, P. Kazarian, V. Maruri, T. Ngai, J. Park, R. Patel, B. Pedersen, J. Schleicher, and S. Shumarayev, quot;Interconnect enhancements for a high-speed PLD architecture,quot; in Proc. ACM/SIGDA Int. Symp. FPGAs, Monterey, CA, 2002, pp. 3-10.
29. Univ. California, Berkeley, quot;Berkeley predictive technology model,quot; 2004. [Online]. Available: http://www.device.eecs.berkeley.edu/ ∼ptm/
30. N. Azizi and F. Najm, quot;An asymmetric SRAM cell to lower gate leakage,quot; in Proc. IEEE Int. Symp. Quality Electron. Des., San Jose, CA, 2004, pp. 534-539.
31. C. Kim, J.-J. Kim, S. Mukhopadhyay, and K. Roy, quot;A forward body-biased low-leakage SRAM cache: Device and architecture considerations,quot; in Proc. ACM/IEEE Int. Symp. Low-Power Electron. Des., Seoul, Korea, 2003, pp. 6-9.
32. Xilinx, Inc., San Jose, CA, quot;Virtex-5 FPGA data sheet,quot; 2007.
33. A. Agarwal, C. Kim, S. Mukhopadhyay, and K. Roy, quot;Leakage in nano-scale technologies: Mechanisms, impact and design considerations,quot; in Proc. ACM/IEEE Des. Autom. Conf., San Diego, CA, 2004, pp. 6-11.
34. S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, quot;Scaling of stack effect and its application for leakage reduction,quot; in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., Huntington Beach, CA, 2001, pp. 195-200.