A 12 Gbps DES encryptor/decryptor core in an FPGA

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1965, Issue , 2000, Pages 156-163

  Trimberger, Steve ^a   Pang, Raymond ^a   Singh, Amit ^b  

^a XILINX INC   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; HARDWARE; INTEGRATED CIRCUIT DESIGN;

CYCLE BASIS; DATA ENCRYPTION STANDARD; DATA RATES; HIGH SPEED IMPLEMENTATION; PHYSICAL CONSTRAINTS; SYNTHESIS TOOL; VERILOG HDL;

CRYPTOGRAPHY;

EID: 68549132277     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: None     Document Type: Conference Paper

References (8)

1. ANSI, “Triple Data Encryption Algorithm Modes of Operation”, American National Standards Institute X9.52-1998, American Bankers Association, Washington DC, July 29, 1998
2. FIPS, “Data Encryption Standard”, Federal Information Processing Standards Publication 46-2, 1993 December 30.
3. FreeIP, http://www.free-ip.com/DES/index.html
4. Kwan, M., “Bitslice DES”, http://www.darkside.com.au/bitslice/nonstd.c
5. Patterson, C., “High Performance DES Encryption in Virtex FPGAs using Jbits”, FCCM 2000, IEEE Computer Society, 2000.
6. Patterson, C., private communication, 2000.
7. Schneier, B., Applied Cryptography, John Wiley and Sons, 1996.
8. Wilcox, D.C., et al., “A DES ASIC suitable for network encryption at 10Gbps and beyond”, First International Workshop on Cryptographic Hardware and Embedded Systems, 1999.