Leakage-Aware Multiprocessor Scheduling

Journal of Signal Processing Systems

Volumn 57, Issue 1, 2009, Pages 73-88

  De Langen, Pepijn ^a   Juurlink, Ben ^a  

^a Delft University of Technology ^*  (Netherlands)

Author keywords

Leakage power; Multiprocessor; Scheduling; Voltage scaling

Indexed keywords

CRITICAL PATH LENGTHS; DIFFERENT FREQUENCY; DYNAMIC POWER CONSUMPTION; DYNAMIC VOLTAGE SCALING; EMBEDDED MULTIPROCESSORS; ENERGY REDUCTION; FUTURE TECHNOLOGIES; LEAKAGE POWER; LOWER BOUNDS; MULTI PROCESSOR SCHEDULING; MULTIPROCESSOR; OPTIMAL NUMBER; PARALLEL APPLICATION; PEAK PERFORMANCE; SCHEDULING HEURISTICS; STATIC POWER CONSUMPTION; TASK GRAPH; THEORETICAL LIMITS; TOTAL ENERGY CONSUMPTION; VOLTAGE SCALING;

BENCHMARKING; CONTROL THEORY; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; MULTIPROCESSING SYSTEMS; VOLTAGE STABILIZING CIRCUITS;

SCHEDULING ALGORITHMS;

EID: 68149164601     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-008-0176-8     Document Type: Article

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