HW/SW methodologies for synchronization in FPGA

Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09

Volumn , Issue , 2009, Pages 265-268

  Tumeo, Antonino ^a   Pilato, Christian ^a   Palermo, Gianluca ^a   Ferrandi, Fabrizio ^a   Sciuto, Donatella ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

Design; Experimentation; Performance

Indexed keywords

ALTERNATIVE DESIGNS; EXPERIMENTATION; MULTIPROCESSOR SYSTEMS ON CHIPS; PERFORMANCE; PROTOTYPING; QUEUING MECHANISM; SOFT-CORE PROCESSORS; SYNCHRONIZATION MODULES;

FAULT TOLERANCE; LOGIC GATES; MACHINE DESIGN; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; QUALITY ASSURANCE; SYNCHRONIZATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 67650671575     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508128.1508174     Document Type: Conference Paper

References (9)

1. John M. Mellor-Crummey and Michael L. Scott. Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Transactions on Computer Systems, 9(1):21-65, 1991.
2. Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. Nios II Core Implementation Details, v8.0.0 edition, 2008. http://www.altera.com.
3. ARM Cortex-M1 processor. Available at http://www.arm.com/products/CPUs/ ARM-Cortex-M1.html.
4. MicroBlaze Processor Reference Guide. Xilinx Corporation.
5. Research Accelerator for Multiple Processors (RAMP), http://ramp.eecs. berkeley.edu/.
6. Xilinx embedded developer kit (EDK). Xilinx Corporation.
7. Designing Multiprocessor Systems in Platform Studio, WP262 (v2.0) November 21, 2007, Xilinx Corporation.
8. XPS Mutex (v1.00a). DS631 february, 20, 2008, Xilinx Corporation.
9. A. Tumeo et al. A Design Kit for a FullyWorking Shared Memory Multiprocessor on FPGA. In Proc. of (GLVLSI), pages 219-222, 2007. (Pubitemid 47469732) (Pubitemid 47469732)