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Volumn 49, Issue 8, 2009, Pages 924-933

SCRAP: Sequential circuits reliability analysis program

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; FAILURE PROBABILITY; FAILURE RATE; FLIGHT CONTROL; INTEGRAL PART; LIFE-CRITICAL APPLICATIONS; RAPID GROWTH; STANDARD CELL; SYSTEM DESIGN PROCESS; TOOLS AND TECHNIQUES;

EID: 67650495198     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2009.06.001     Document Type: Article
Times cited : (20)

References (22)
  • 2
    • 0142184763 scopus 로고    scopus 로고
    • Cost-effective approach for reducing soft error failure rate in logic circuits
    • Mohanram K, Touba, NA. Cost-effective approach for reducing soft error failure rate in logic circuits. In: Proceedings of ITC; 2003. p. 893-901.
    • (2003) Proceedings of ITC , pp. 893-901
    • Mohanram, K.1    Touba, N.A.2
  • 4
    • 0028457094 scopus 로고
    • RSYN: a system for automated synthesis of reliable multilevel circuits
    • De K., Natarajan C., Nair D., and Banerjee P. RSYN: a system for automated synthesis of reliable multilevel circuits. IEEE Trans VLSI Syst (1994) 186-195
    • (1994) IEEE Trans VLSI Syst , pp. 186-195
    • De, K.1    Natarajan, C.2    Nair, D.3    Banerjee, P.4
  • 8
    • 2942630757 scopus 로고    scopus 로고
    • NANOPRISM: A tool for evaluating granularity versus reliability trade-offs in nano architectures
    • Bhaduri D, Shukla S. NANOPRISM: a tool for evaluating granularity versus reliability trade-offs in nano architectures. In: Proceedings of the 14th ACM Great Lakes symposium on VLSI; 2004. p. 109-12.
    • (2004) Proceedings of the 14th ACM Great Lakes symposium on VLSI , pp. 109-112
    • Bhaduri, D.1    Shukla, S.2
  • 10
    • 0037565605 scopus 로고
    • Multiterminal binary decision diagrams: An efficient data structure for matrix representation
    • Presented at the, Tahoe City, CA; 23-26 May, unpublished
    • Clarke E, Fujita M, McGeer P, Yang J, Zhao X, Multiterminal binary decision diagrams: an efficient data structure for matrix representation. Presented at the international workshop on logic synthesis (IWLS), Tahoe City, CA; 23-26 May, 1993, unpublished.
    • (1993) international workshop on logic synthesis (IWLS)
    • Clarke, E.1    Fujita, M.2    McGeer, P.3    Yang, J.4    Zhao, X.5
  • 11
    • 0017983865 scopus 로고
    • Binary decision diagrams
    • Akers S.B. Binary decision diagrams. IEEE Trans Comput c-27 6 (1978)
    • (1978) IEEE Trans Comput , vol.c-27 , Issue.6
    • Akers, S.B.1
  • 17
    • 11344251915 scopus 로고    scopus 로고
    • Improving gate-level simulation of quantum circuits
    • Viamontes G.F., Markov I.L., and Hayes J.P. Improving gate-level simulation of quantum circuits. Quantum Inf Process 2 5 (2003) 347-380
    • (2003) Quantum Inf Process , vol.2 , Issue.5 , pp. 347-380
    • Viamontes, G.F.1    Markov, I.L.2    Hayes, J.P.3
  • 18
    • 0018524018 scopus 로고
    • Controllability/observability analysis of digital circuits
    • Goldstein L.H. Controllability/observability analysis of digital circuits. IEEE Trans Circuits Syst CAS26 September (1979) 685-693
    • (1979) IEEE Trans Circuits Syst , vol.CAS26 , Issue.September , pp. 685-693
    • Goldstein, L.H.1
  • 20


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.