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Volumn , Issue , 2008, Pages 890-893

Programmable high density CMOS microelectrode array

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG MEMORIES; BIOLOGICAL CELLS; CMOS PROCESS; DEVICE MISMATCH; HIGH DENSITY; IN-VITRO; INHOMOGENEITY; MICROELECTRODE ARRAY; NON-VOLATILE; PROCESS VARIATION;

EID: 67649996375     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSENS.2008.4716584     Document Type: Conference Paper
Times cited : (3)

References (9)
  • 1
    • 9144251670 scopus 로고    scopus 로고
    • A 128 × 128 CMOS biosensor array for extracellular recording of neural activity
    • B. Eversmann et al., "A 128 × 128 CMOS biosensor array for extracellular recording of neural activity," IEEE J. Solid-State Circuits, vol.38, pp. 2306-2317, 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , pp. 2306-2317
    • Eversmann, B.1
  • 4
    • 57649156157 scopus 로고    scopus 로고
    • Cell recordings with a CMOS high density microelectrode array
    • Aug. 23-26
    • U.Frey, et al., "Cell recordings with a CMOS high density microelectrode array," IEEE EMBS, Aug. 23-26, 2007, pp. 167-170.
    • (2007) IEEE EMBS , pp. 167-170
    • Frey, U.1
  • 6
    • 33748559073 scopus 로고    scopus 로고
    • High-resolution multitransistor array recording of electrical field potentials in cultured brain slices
    • DOI 10.1152/jn.00347.2006
    • M. Hutzler et al., "High-resolution multitransistor array recording of electrical field potentials in cultured brain slices," J Neurophysiol, vol.96, no. 3, pp. 1638-1645, 2006. (Pubitemid 44371550)
    • (2006) Journal of Neurophysiology , vol.96 , Issue.3 , pp. 1638-1645
    • Hutzler, M.1    Lambacher, A.2    Eversmann, B.3    Jenkner, M.4    Thewes, R.5    Fromherz, P.6
  • 7
    • 0022863439 scopus 로고
    • Implantable multielectrode array with on-chip signal processing
    • K. Najafi and K. Wise, "An implantable multielectrode array with onchip signal processing," IEEE J. Solid-State Circuits, vol.21, pp. 1035-1044, 1986. (Pubitemid 17500540)
    • (1986) IEEE Journal of Solid-State Circuits , vol.SC-21 , Issue.6 , pp. 1035-1044
    • Najafi Khalil1    Wise Kensall, D.2
  • 8
    • 0036294819 scopus 로고    scopus 로고
    • A simulation model for floating gate synapse transistors
    • K. Rahimi, C. Diorio, C. Hernandez, M. Brockhausen, "A simulation model for floating gate synapse transistors," IEEE ISCAS 2002, pp. 532-535.
    • (2002) IEEE ISCAS , pp. 532-535
    • Rahimi, K.1    Diorio, C.2    Hernandez, C.3    Brockhausen, M.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.